3 ms·

Another way of saying this that I think is somewhat more accurate is that they're constrained by designing for an acceptable transistor budget, which sort of co

Another way of saying this that I think is somewhat more accurate is that they're constrained by designing for an acceptable transistor budget, which sort of correlates to a particular node. IIRC, Apple's chips are _significantly_ larger in terms of transistor count than their competitor's chips. A design that uses an equivalent # of transistors - a very messy and inaccurate proxy for a requirement for perf parity - would likely price it out of the range of most phone manufacturers unless built on the newest process. Frankly, it may not be an acceptable cost even at the newest node - Apple seems willing to spend a bit more on their chips than most, and likely gets better prices in any case due to the size of their orders.

pdpi 4y ago
> A design that uses an equivalent # of transistors - a very messy and inaccurate proxy for a requirement for perf parity At some point it got twisted into "double the speed", but Moore's Law as originally formulated was precisely about this - doubling transistor count.
- Symmetry 4y ago
  It wasn't really a matter of twisting. The phrase "Moore's Law" got coined in an interview at the same 1975 conference where Dennard presented on his scaling laws and has never referred just to the first periodic doubling Moore noted in his 1965 paper.
  - vlovich123 4y ago
    Back then, the transistor switching speed was 1:1 correlated with size and the sizes we're talking about then the size dominated (capacitance between gate & source). That decoupled in the late 90s / early 00s (if my recollection of news is correct) & kept getting more decoupled. These days you can have a switching speed of 604 Ghz but that doesn't translate to overall clock speed (dominated by critical path latency of your pipeline) + there's thermal issues. Disclaimer: Not an EE / HW designer. Going off of memory from tech news + some university courses (info may be incorrect / stale).
    - Symmetry 4y ago
      It was more that leakage current (i.e. thermal issues) and velocity saturation suddenly becoming constraints on how much you could increase switching speed along with the difficulty of high frequency clock distribution. Your individual transistor switching speed is always going to be a lot faster than your clock speed because a pipeline stage has to be made up of many layers of transistors to get anything useful done (including latch the signal at the clock edge!) and each transistor will typically drive multiple others. I was seriously considering being a chip engineer for a while and did my master's thesis on adder design.
      - mardifoufs 4y ago
        What made you change your mind?
        Symmetry 4y ago
        Realizing that I'd be a small cog in a large team for most of my career down that path.
tyingq 4y ago
Another example might be this Cortex-X3 being the first in ARM's X line to drop the 32 bit ISA, where Apple had dropped that in the A11. That gave Apple several iterations to take advantage of whatever simplifications or reclaimed transistor budget came from dropping it. Edit: Small miss above...Cortex-X2 dropped aarch32, though that's 2021 versus Apple doing it in 2017 with the A11, so the overall point is the same.
- kramerger 4y ago
  Hasn't aarch32 always been optional in armv8? I mean, technically you can emulate it in software. It was simply no market for solo aarch64 before, since a lot of costumers wanted the backup of having aarch32 compatibility.
- gsnedders 4y ago
  Cortex-X2 dropped A32 & T32.
  - tyingq 4y ago
    Ah...yep, I was was wrong there. Though still much later than the Apple/A11...2017 vs 2021. What the article says on this topic: "The process of eliminating 32-bit and optimizing for the 64-bit ISA exclusively has been a 2-step process. With the Cortex-X2, the underlying circuitry used for handling 32-bit architectural-related elements was removed, saving on transistors and simplifying some structures. With the new Cortex-X3, the design team took the time to start optimizing specifically for AArch64."

pdpi 4y ago

> A design that uses an equivalent # of transistors - a very messy and inaccurate proxy for a requirement for perf parity At some point it got twisted into "double the speed", but Moore's Law as originally formulated was precisely about this - doubling transistor count.

Symmetry 4y ago
It wasn't really a matter of twisting. The phrase "Moore's Law" got coined in an interview at the same 1975 conference where Dennard presented on his scaling laws and has never referred just to the first periodic doubling Moore noted in his 1965 paper.
- vlovich123 4y ago
  Back then, the transistor switching speed was 1:1 correlated with size and the sizes we're talking about then the size dominated (capacitance between gate & source). That decoupled in the late 90s / early 00s (if my recollection of news is correct) & kept getting more decoupled. These days you can have a switching speed of 604 Ghz but that doesn't translate to overall clock speed (dominated by critical path latency of your pipeline) + there's thermal issues. Disclaimer: Not an EE / HW designer. Going off of memory from tech news + some university courses (info may be incorrect / stale).
  - Symmetry 4y ago
    It was more that leakage current (i.e. thermal issues) and velocity saturation suddenly becoming constraints on how much you could increase switching speed along with the difficulty of high frequency clock distribution. Your individual transistor switching speed is always going to be a lot faster than your clock speed because a pipeline stage has to be made up of many layers of transistors to get anything useful done (including latch the signal at the clock edge!) and each transistor will typically drive multiple others. I was seriously considering being a chip engineer for a while and did my master's thesis on adder design.
    - mardifoufs 4y ago
      What made you change your mind?
      - Symmetry 4y ago
        Realizing that I'd be a small cog in a large team for most of my career down that path.

tyingq 4y ago

Another example might be this Cortex-X3 being the first in ARM's X line to drop the 32 bit ISA, where Apple had dropped that in the A11. That gave Apple several iterations to take advantage of whatever simplifications or reclaimed transistor budget came from dropping it. Edit: Small miss above...Cortex-X2 dropped aarch32, though that's 2021 versus Apple doing it in 2017 with the A11, so the overall point is the same.

kramerger 4y ago
Hasn't aarch32 always been optional in armv8? I mean, technically you can emulate it in software. It was simply no market for solo aarch64 before, since a lot of costumers wanted the backup of having aarch32 compatibility.
gsnedders 4y ago
Cortex-X2 dropped A32 & T32.
- tyingq 4y ago
  Ah...yep, I was was wrong there. Though still much later than the Apple/A11...2017 vs 2021. What the article says on this topic: "The process of eliminating 32-bit and optimizing for the 64-bit ISA exclusively has been a 2-step process. With the Cortex-X2, the underlying circuitry used for handling 32-bit architectural-related elements was removed, saving on transistors and simplifying some structures. With the new Cortex-X3, the design team took the time to start optimizing specifically for AArch64."