5 ms·
Moving ram over to pcie makes a lot of sense. Glad that’s on the roadmap.
by nynx 4y ago
Moving ram over to pcie makes a lot of sense. Glad that’s on the roadmap.
- skavi 4y agowhat would ram over pcie help with?
- voxadam 4y agoI'm no expert but I bet some users would enjoy RAM over a switchable PCIe fabric. They'd take a latency hit but would have the potential for massive amounts of memory.
- pbalcer 4y agoMany things. Capacity, Bandwidth, Serviceability [1]. It also paves the road towards disaggregated memory [2]. edit: The official Compute Express Link (CXL) website has an article about the benefits of this technology [3]. [1] - https://www.nextplatform.com/2021/09/07/the-cxl-roadmap-opens-up-the-memory-hierarchy/ https://www.nextplatform.com/2021/09/07/the-cxl-roadmap-open... [2] - https://pmem.io/blog/2022/01/disaggregated-memory-in-pursuit-of-scale-and-efficiency/ https://pmem.io/blog/2022/01/disaggregated-memory-in-pursuit... [3] - https://www.computeexpresslink.org/post/the-benefits-of-serial-attached-memory-with-compute-express-link https://www.computeexpresslink.org/post/the-benefits-of-seri...
- teaearlgraycold 4y agoIt'd be interesting to see a desktop system with almost everything running over PCIe. You could drop the chipset entirely at that point.
- toast0 4y agoAmd's A300 and X300 chipsets for AM4 are just a bit of rom. Modern CPUs don't really need a chipset; AM4 chipsets connect to the CPU through PCIe, anyway.
- kalleboo 4y agoWe'll be right back in the S-100 bus days
- matja 4y agoAMD EPYC is already that, a SoC - there is no EPYC chipset. They all have 8x 16-lane multi-function interfaces, which can be configured to work as PCIe, xGMI (inter-socket communucation), or SATA, as well as built-in USB, eMMC, LPC, UART, I2C, SMBus, GPIO.
- undersuit 4y agoYeah, but somebody might insist that the IO-die means that the chipset has moved onto the CPU but still exists.
- jleahy 4y agoThe latency is going to be much too high, when the performance numbers turn up people will decide they don’t want it. A similar thing happened with Intel Optane (which is now dying).
- rbanffy 4y agoMemory latency is only bad when you have a cache miss. That’s why mainframes have gigabytes of cache between their processors and memory. You can mitigate that with some in-package HBM. IIRC, Xeon Phis came with up to 16GB of it - you could in theory have a workstation without any memory sticks.
- Dylan16807 4y agoI would hope and expect that CXL gets latency low enough to make it viable. These days you're mostly waiting for the core of the ram chips to respond as everything else races around it. For Optane, I'd say it's doing so badly because it's barely cheaper than RAM, which means it's only useful in niche situations.
- rbanffy 4y agoThere’s IBM’s OMI as well. https://openmemoryinterface.org/ https://openmemoryinterface.org/
- Lramseyer 4y agoI think there are a lot of misconceptions here in other sub comments. For starters, the DRAM manufacturers may possibly be the biggest penny pinchers in the semiconductor business. They're too cheap to use differential signaling even on GDDR memory. I'm not saying that PCIe RAM is never going to happen, but as somebody who works with DRAM controllers and DRAM vendors, I can not fathom a world where DRAM manufacturers put a PCIe controller on each chip, especially one capable of Gen 6.0 speeds! The extra die area, complexity, and bringup testing necessary for a PCIe controller is insane Second of all, the latency would really destroy system performance. The DDR protocol is designed to minimize latency (well kind of, there are still speed targets that need to be met.) The whole point of using a parallel bus with unscrambled data is to eliminate encoding/decoding latency. PCIe uses a Serializer/Deserializer (SerDes) that's scrambled on one end and then de-scrambled on the other end using a LFSR. It also goes through an adaptive tap filter. After that, the ordered sets from each lane are assembled and sent through a FIFO for clock domain crossing/timing recovery. All of those steps add latency to the system, and that's before we get to the Data Link Layer and Transaction layer. While I'm not well versed in CXL, I know that it shares the same Physical layer (a SerDes Phy.) Now you might imagine a chip with one PCIe end point that fans out to an array of DRAM chips on the back end, and you don't care that much about latency. But then that makes PCIe RC and EP in the system redundant because you could put the DRAM controller where you would otherwise put the PCIe controller. Now it might make packaging easier and allow for a cheaper version of DDR to be implemented, but is there a net savings? and does it justify the latency hit? Maybe. I'm not saying it's never going to happen, but I wouldn't bet on that tech.