4 ms·
Some of these are standard, a few are genuinely clever, but many are bad designs and I'd never let someone tape them out in production. 2. Connecting the body
by kayson 4y ago
Some of these are standard, a few are genuinely clever, but many are bad designs and I'd never let someone tape them out in production.
2. Connecting the body terminal to something other than the highest voltage is dangerous and we rarely do it except in switches and diff pairs. We'd never do something like this. You can't even connect the nmos body to the gate unless you're using "deep" nwells which is an expensive process step that most people seem to avoid these days
3. I hate it when foundries do this in their standard cell libraries. Its an extremely weak pulldown and I've seen problems in production caused by using this structure. You can make a much better structure with a third transistor and positive feedback where devices still aren't connected to the supplies, but you get a stronger pull.
4-6. These are current-mode logic, but you never see them made this way because they're slow and high power. Instead they're usually made with a tail current source on the "bottom" and resistors on top, which keeps all transistors in a faster operating region. They get used often in RF clock dividers.
16. Again, connecting the body is dangerous, especially when the potential is somewhat unknown, but this does get used in extremely low power/low voltage applications.
I didn't get through all of them, but it made me wonder - with two 4-terminal devices, how many possible configurations can you actually make?
- mzs 4y agoWhich are clever?
- kayson 4y ago18 is cool. Folding is a really under-rated and under-utilized technique. Common-gate impedance matching is "standard", but 22 uses it to also generate differential current outputs which is cool - I imagine it sees more use in RF design. 23 is also interesting. 27 blew my mind. I'm not familiar with ultra low power techniques so that was cool to see.
- yababa_y 4y agoThe paper cites https://ieeexplore.ieee.org/abstract/document/8506644 https://ieeexplore.ieee.org/abstract/document/8506644, which enumerates 582 possible topologies for two transistors, and 56280 for three. I imagine most are useless and/or dangerous.
- amelius 4y ago> a few are genuinely clever Another perspective is that it would take a computer only a few minutes to generate all these circuits and test them for usefulness in a simulator.
- kayson 4y agoThat's harder than you might think. How would you test for all possible uses? Even if you looked at something fundamental like an N-port, you'd still have to define metrics for usefulness and many of the topologies in the paper would evade most obvious circuit metrics.
- amelius 4y agoWell, you are right to some extent, but in practice you don't need "all possible uses" and instead you are looking for a specific behavior, which you can easily encode in a test that uses a simulator.
- ajnin 4y agoThe article mentions that circuit 23 was found using an "exhaustive search", so presumably using an automated means. But I don't think that works in the general case to find all "useful" circuits. For example figure 27 is a pA source and requires 2 precise control voltages and a clock source. 39 is a peak detector. Does not seem that easily encoded.