12 ms·

The Worst CPUs Ever Made (2021)

88 points by fzliu 4y ago

easytiger 4y ago
My first PC had a cyrix 333Mhz CPU. Ran just fine! But I was learning c in Borland turbo c and djgpp so it didn't have to do much. Running java on it... Well that wasn't fun with the 32MB RAM. Worked on itanium too. It was more amazing Microsoft actually had support for it.
velcrovan 4y ago
CTRL+F "transmeta crusoe": Not found ah well
- mrintellectual 4y ago
  My vote for worst CPU goes to the iAPX 432 (also not on this list).
  - Max-q 4y ago
    When I saw the headline I expected the iAPX to be number one on the list.
  - sidewndr46 4y ago
    I was looking for this as well. It should be on there for introducing a completely new architecture, costing more, and underperforming contemporary products from Intel's catalog.
  - jandrese 4y ago
    Wow, a garbage collector implemented inside of the processor. Chip level support for objects. You can't fault Intel for their ambition here, just their common sense. And the whole thing is built for a world where everybody is writing code in Ada. I bet some compiler makers were salivating at the prospect of collecting all of those huge license fees from developers.
    - Taniwha 4y ago
      It was a different time - memory/CPU speed trade-offs were very different - we saw RISC once we were able to move cache on-chip (or very very close) - but at that point CISC made sense and the 432 pushed CISC to the extreme. IMHO the x86 won out (an d is still with us) because of all the CISCs of its time it was the closest to RISC when memory started to get a lot faster (almost all instructions make at most 1 memory access, few esoteric memory operations etc)
      - Thetawaves 4y ago
        All instructions take at least 1 memory access. All instructions that do memory access need at least 2 memory accesses.
    - p_l 4y ago
      I once encountered a note from one of the people working on iAPX 432, claiming that the core idea of high level cpu wasn't really the issue it tanked, but project mismanagement and horrible design applied which resulted in a chip that would be technologically at home... In 1960s, just done in VLSI - one of the things I recall were issues with actual physical implementation of the memory data paths resulting in horrible IPC
  - ncmncm 4y ago
    Isn't the i860 the inheritor of iAPX 432 design details?
- UmbertoNoEco 4y ago
  Oh those were the days were I was young and naive and I thought Linus was going to change the world (again) blurring the lines between 'software' and 'hardware'
- hajile 4y ago
  I think transmeta was MUCH better than Itanium. Itanium held the idea that we could accurately predict ILP at compile time (when the halting problem clearly states that we cannot). Transmeta said VLIW has the best theoretical PPA possible, so let's wrap that in a large, programmable JIT to analyze/optimize stuff to take advantage. Modern CPUs run quite a bit closer to transmeta, but they largely use fixed-function hardware rather than being able to improve performance at a later time. If we could nail down that ideal VLIW architecture, we could sell a given chip at various process sizes and then offer various paid "software" upgrades or compatibility packs for various ISAs to run legacy code. At least there's a pipe dream worth looking into.
  - cogman10 4y ago
    > Itanium held the idea that we could accurately predict ILP at compile time (when the halting problem clearly states that we cannot). I don't know where these notions are coming from. Compilers can (and do) reorder instructions to extract as much parallelism as possible. Further, SIMD has forced most compilers down a path of figuring out how to parallelize, at the instruction level, the processing of data. Further, most CPUs now-a-days are doing instruction reordering to try and extract as much instruction level parallelism out as possible. Figuring out what instructions can be run in parallel is a data dependency problem, one that compilers have been solving for years. Side note: the instruction reordering actually poses a problem for parallel code. Language writers and compiler writers have to be extra careful about putting up "fences" to make sure a read or write isn't happening outside a critical section when it shouldn't be.
    - p_l 4y ago
      The critical difference is that EPIC (the architecture model of Itanium) essentially exposed CPU pipelines naked to the code - so you didn't just have to reorder instructions as optimizers do today, you also had to figure out changes that experience so far suggests is doable either in hw with runtime-only data, or in very tight numerical code. This includes compiler taking the place of branch predictor as well as OOOE scheduling, as well as no on-cpu instruction reordering or out of order retirement, and IIRC a branch mispredict was quite costly. More over, EPIC pretty much meant thar you couldn't apply similar chip-level IPC improvements as you could elsewhere, at least originally.
- deleted 4y ago
  [deleted]
- pengaru 4y ago
  I had a Transmeta Crusoe based PC104 SBC and for the time it was relatively quick for something low power, does it really deserve to be in the "worst cpus ever" list? why for?
  - velcrovan 4y ago
    You’re right. I was kind of being snarky. But it was a huge disappointment compared against the promises from Transmeta and the tech journalism of the time.
nesarkvechnep 4y ago
Cyrix wasn't the first company to build SoC, Acorn was.
- fanf2 4y ago
  You are referring to the ARM 250 chip in the Acorn A3010, A3020, and A4000 https://en.wikipedia.org/wiki/Acorn_Archimedes https://en.wikipedia.org/wiki/Acorn_Archimedes
  - nesarkvechnep 4y ago
    Yes, thank you!
masklinn 4y ago
The lack of Alpha seems odd, though maybe that should be the worst ISA rather than merely individual CPU?
- pinewurst 4y ago
  Why would Alpha be the worst? I’ve owned 2 of them, 21064 and 21264, and they were fast and reliable.
  - als0 4y ago
    The influence of Alpha on modern instruction sets like ARM64 and RISC-V is tremendous. It’s just sad it had to die for this to happen.
    - scrlk 4y ago
      I'd also add that a lot of excellent ex-Alpha engineers (e.g. Jim Keller, Dan Dobberpuhl off the top of my head) ended up designing great chips at other companies.
    - hajile 4y ago
      It didn't die. Intel bought it from HP, stripped it for parts, then killed it. HyperTransport and a few other things were essentially just copies of Alpha's stuff cleanroom implemented by ex-Alpha employees. Designs like Sandy Bridge look quite similar to EV8. QuickPath is just Alpha's interconnect with some updates (HyperTransport was also a cleanroom copy from ex-Alpha employees). Even AVX seems inspired by the 1048-bit SIMD planned for EV9/10.
    - jeffbee 4y ago
      How did the Alpha ISA influence RISC-V, other than by its counterexample? Does RISC-V lack an integer divide? "Design of the RISC-V Instruction Set Architecture" mainly uses Alpha in the phrase "Unlike Alpha, ..." i.e. as a warning to future people. In fact, the author fairly well excoriates all of the historic RISC architectures for being myopically designed.
xbar 4y ago
I'm so ashamed to have owned a Cyrix, a P4, and an AMD Bulldozer. They were all awful.
- josteink 4y ago
  I’ve had a P4 and I didn’t consider it “awful”. It was without a doubt the fastest CPU I had ever had at the time, but boy did it generate heat and need cooling. That machine sounded like a always on vacuum-cleaner.
  - sidewndr46 4y ago
    I owned a Pentium 4 as well (oh boy did I save for a long time as a teenager to afford that). It wasn't really as bad as what this article claims. On the other hand, the dual-core parts probably really are that bad.
    - jandrese 4y ago
      The article did call out in particular the late generation P4s with the super duper extra long pipeline that simply couldn't keep themselves fed when working with anything but synthetic benchmarks.
- zepearl 4y ago
  Intel was too expensive for me, so I ended up buying a Cyrix => performance (floating point) was terrible in Falcon 3, I was sooo sad - but on the other hand that gave me until today the push to really focus on details before taking a decision => thank you Cyrix for having changed my life hehe.
- pseudosavant 4y ago
  I had two Bulldozers. Bulldozer wasn't competitive at the top end, but I always found Athlon chips to be cheaper than their performance equivalent Intel part. So the fastest AMD chip would be cheaper than the third fastest Intel part. Still a good value. Terrible for AMD's bottom-line though.
hajile 4y ago
This doesn't seem to be the best-researched article out there. If they thought Itanium was bad, they should have looked into the i860. Itanium was an attempt to fix a bunch of the i860 ideas. i860 quickly went from a supercomputer chip to a cheap DSP alternative (where it had at least the hope of hitting more than 10% of its theoretical performance). Intel iAPX 432 was preached as the second coming back in the 80s, but failed spectacularly. The i960 was take 2 and their joint venture called BiiN also shuttered. Maybe Rekursiv would be worthy of a mention here too. We now know that core 2 dropped all kinds of safety features resulting in the Meltdown vulnerabilities. It also partially explains why AMD couldn't keep up as these shortcuts gave a big advantage (though security papers at the time predicted that meltdown-style attacks existed due to the changes). Rather than an "honorable mention", the Cell processor should have easily topped the list of designs they mentioned. It was terrible in the PS3 (with few games if any able to make full use of it) and it was terrible in the couple supercomputers that got stuck with it. I'd also note that Bulldozer is also maligned more than it should be. There's a lot to like about the concept of CMT and for the price, they weren't the worst. I'd even go so far as to say that if AMD wasn't so starved for R&D money during that period, they may have been able to make it work. ARM's latest A510 shares more than a few similarities. A big/little or big/little/little CMT architecture seems like a very interesting approach to explore in the future.
- causality0 4y ago
  Yes, and no mention of the Transmeta Crusoe either.
- the_only_law 4y ago
  > The i960 was take 2 and their joint venture called BiiN also shuttered. I have an old X-11 terminal I believe has a i960 in it. I’m shocked that thing was capable of running CDE desktops when it stutters on FVWM over a network much faster than it ever was intended to see.
- notacoward 4y ago
  At least the 960 was somewhat usable. Many variants were created, and several were widely used in embedded products for quite a few years. The 860, however, was Just Crap. Full stop. End of story. IIRC it had weird double-instruction modes that compilers just couldn't handle, and if you used them anyway (for very necessary performance) then handling exceptions properly was all but impossible. Definitely gets my vote for worst ever.
SeanLuke 4y ago
What does "worst CPU" mean? I think that it means, regardless of market success, the CPU that most hindered, indeed retarded, progress in CPU engineering history. In this regard, #1 and #2 are clearly the 8088 and 80286 respectively.
- als0 4y ago
  Agreed. I think Itanium gets a lot of unnecessary slack. It really tried some exciting new ideas and clean concepts. Not all of those concepts were much of a win, but with the first chip arriving years late then there’s no wonder it was perceived as underwhelming from the get go (that would happen to any chip that’s late)
  - cogman10 4y ago
    Funnily, I feel like SIMD instructions are slowly reinventing what the itanium did out of the box. I think a modern compiler could likely do a good job with itanium now-a-days. However, when it first came out, there simply wasn't the ability to keep those instruction batches full. Compiler tech was too far behind to work well with the hardware.
    - zamadatix 4y ago
      I'm not sure I'd say many compilers are even that great with SIMD these days and that is easier than what the itanium was asking of compilers. There are real gains to be had by using SIMD but it tends to be massively parallel data processing workloads with specially written SIMD code or even hand tuned assembly (image/video processing, neural networks) not just feeding in a source file and compiling with the SIMD flag to then realize meaningful gains.
      - cogman10 4y ago
        The reverse is true. SIMD is harder because you have to have a uniform operation across a set of data. Imagine a for loop that looks like this int[] x, y, z; int[] p, d, q; for (int i = 0; i < size; ++i) { p[i] = x[i] / z[i] d[i] = z[i] * x[i] q[i] = y[i] + z[i] } For SIMD, this is a complicated mess for the compiler to unravel. What the compiler would LIKE to do is turn this into 3 for loops and use the SIMD instructions to perform those operations in parallel. The itanium optimization, however, is a lot easier. The compiler can see that none of p, d, or q depend on the results of the previous stage (that is q[i] doesn't depend on p[i]). As a result, the entire thing can be packed into a single operation. Now, of course, modern OOO processors can do the same optimization so maybe it's not a huge win? Still, would have been something worth exploring more (IMO) but the market forces killed it. Moving that sort of optimization out of the processor hardware and into the compiler software seems like it could lead to some nice power/performance benefits.
tangental 4y ago
I visted this page hoping to see the PowerPC 970 top of the list, but all it gets is a "Dishonorable Mention". After going through three PowerMac G5s, all of which had their processors die within 4 years, I still bear a grudge.
- sidewndr46 4y ago
  For us non Apple users, how is that possible? I don't think I've ever had a CPU die other than by lightning.
  - kzrdude 4y ago
    I was imagining lightning struck the cpu specifically, leaving the rest intact? Quite the precision.
    - sidewndr46 4y ago
      Oh no, the last time this happened there were definitely other casualties. The motherboard was left in a particular state of undeath, where it wouldn't quite power on. But if you jumped the ATX header it'd sort of attempt to boot and give some beeps. After that I added a bunch of grounding to my house and I haven't had that much damage in one lightning strike before.
  - giantrobot 4y ago
    I don't know what OP was running but the G5 iMacs were some of the machines suffering from the early 2000s capacitor plague[0]. The power supplies and power regulation on the logic boards would die on those all the time. If you were lucky it was just the power supply but the problem usually needed a PSU and logic board swap. [0] https://www.cnet.com/culture/pcs-plagued-by-bad-capacitors/ https://www.cnet.com/culture/pcs-plagued-by-bad-capacitors/
  - pram 4y ago
    The processor in a G5 PowerMac came on a card that had the VRMs, capacitors, and a bunch of other stuff on it. It was basically like a tiny motherboard that attached to your motherboard.
annoyingnoob 4y ago
I've owned 4 or 5 of the CPUs on that list over the years. I'm sure there are worse.
McGlockenshire 4y ago
I'm currently building a homebrew system built on the TMS99105A CPU, one of the final descendants of the TMS9900. It's a nifty little CPU. There's a lot of hidden little features once you dig in. It can actually address multiple separate 64k memory namespaces: data memory, instruction memory, macroinstruction memory, and mapped memory with the assistance of a then-standard chip. Normally these are all the same space and just need external logic to differentiate them. There's also a completely separate serial and parallel hardware interface bus. The macroinstruction ("Macrostore") feature is pretty fun. There's sets of opcodes that will decode into illegal instructions that, instead of immediately erroring out, will go looking for a PC and workspace pointer (the "registers") in memory and jump there. Their commercial systems like the 990/12 used this feature to add floating point and other features like stack operations. Yup, there's no stack. Just the 16 "registers," which live in main memory. There are specific branch and return instructions that store the previous PC and register pointer in the top registers of the new "workspace," allowing you direct access to the context of the caller. The assembly language is simple and straightforward with few surprises, but it's also clearly an abstraction over the underlying mechanisms of the CPU. I believe this then classifies this CPU as CISC incarnate. There are some brilliant and insane people on the Atari Age forums! One of them managed to extract and post the data for a subset of those floating point instructions, and then broke it all down and how it all worked. Some are building new generations of previous TMS9900 systems. One of them is replicating the CPU in an FPGA. A few others are building things like a full-featured text editor and, of course, an operating system. I've learned a hell of a lot during this project. I've been documenting what I'm doing and am planning to eventually make it into a pretty build log. I think this is a beautiful dead platform that deserved better.
- ncmncm 4y ago
  The TI's serial I/O bus takes the prize, for me.
- throwawayboise 4y ago
  I have a soft spot for that CPU. My first computer was a TI99/4a when I was about 14 or 15. I started with BASIC, then learned assembly language on that machine. I give it a lot of credit for starting the trajectory my future took.
alkaloid 4y ago
As a system builder for a "custom computer shop" back in 1997/98, I came here just to make sure Cyrix was on the list.
- gattilorenz 4y ago
  No IDT WinChip though, that's mildly surprising
  - timw4mail 4y ago
    I don't think the Winchip was that well known. But it never pretended to be a high performing design.
    - gattilorenz 4y ago
      The list includes the MediaGX, so I thought it might be comparable in popularity/performance expectations. To be honest, I remember the WinChip because I thought the printed Windows logo on the CPU was pretty cool. Texas and AMD also had the "designed for Windows 95" logo on some of their CPUs (some 486 and Overdrive designs, iirc)
bstar77 4y ago
I would vote for the Pentium IV for all the reasons mentioned in the article, but more importantly because it was initially coupled with Rambus memory. Intel pushed that tech so hard to try and squeeze out AMD. Super high frequency, high bandwidth, high expense memory with terrible latency was not the future anyone wanted. Intel's hubris back then was off the charts. I know intel wanted Itanium to succeed for the same reasons, but the PIV came very close to home since it actually shipped for consumers. Oddly enough, Extreme Tech was a huge shill for Intel back in those days. Funny they don't mention that in this article.
StillBored 4y ago
Man, that 6x86 CPU is still getting the short end of the stick nearly three decades later despite being a pretty solid chip. So, first it generally had a higher IPC than anything else available (ignoring the P6). So, the smart marketing people at cyrix decided they were going to sell it based on a PR rating which was the average performance on a number of benchmarks vs a similar pentium. AKA a Cyrix PR166 (clocked at 133Mhz) was roughly the same perf as a 166Mhz pentium. Now had they actually been selling it for a MSRP similar to a pentium 166 that might have seemed a bit shady, but they were selling it closer to the price of a pentium 75/90. Then along comes quake which is hand optimized for the pentium's U/V pipeline architecture and happens to use floating point too. And since a number of people had pointed out the Cx86's floating point perf was closer in "PR" ratings to its actual clock speed suddenly you have a chip performing at much less than its PR rating, and certain people then proceeded to bring up the fact that it was more like a 90Mhz pentium in quake than a 166Mhz pentium (something i'm sure made, say intel, really happy) at every chance they get. So, yah here we are 20 years later putting a chip with what was generally a higher IPC than its competitors on a "shit" list mostly because of one benchmark. While hopefully all being aware that these shenanigins continue to this day, a certain company will be more than happy to cherry pick a benchmark and talk up their product while ignoring all the benchmarks that make it look worse. Now as far as motherboard compatibility, that was true to a certain extent if you didn't bother to assure your motherboard was certified for the higher bus rates required by the cyrix, and the other being it tended to require more sustained current than the intels the motherboards were initially designed for. So, yah the large print said "compatible with socket7" the fine print later added that they needed to be qualified, and the whole thing paved the way for the super socket7 specs which AMD made use of. And of course lots of people didn't put large enough heatsink/fans on them which they needed to be stable. So, people are shitting on a product that gets a bad rep because they were mostly ignorant of what we have all come to accept as normal business when your talking about differing micro architectural implementations. PS: Proud owner of a 6x86 that cost me about the same as a pentium 75, and not once do I think it actually performed worse than that, while for the most part (compiling code, and running everything else including Unreal) it was significantly better than my roommates pentium75.
- hulitu 4y ago
scrlk 4y ago
A different twist on the Itanium: technically bad but ended up as a strategic win for Intel. SGI, Compaq and HP mothballed development of their own CPUs (MIPS/Alpha/PA-RISC) as they all settled on Itanium for future products. After Itanium turned out to be a flop, those companies adopted x86-64 - Intel killed off 3 competing ISAs by shipping a bad product.
- Melatonic 4y ago
  Interesting take!
- sanguy 4y ago
  Very true, it was the end of the DEC Alpha as Compaq chose the Itanic.
- npunt 4y ago
  Itanium was the OS/2 of chips, Microsoft used OS/2 to get IBM chasing a dead end while they baked Windows NT & 95 until their lead was secured.
grp000 4y ago
For a bit of time, I ran an over clocked FX 8320 and crossfire 7970's. The heat that machine put out was tremendous. I only had a wall mounted AC unit so I had to practically take my shirt off when I loaded it up.
- robotnikman 4y ago
  Ah yes, AMD/ATI crossfire. I had nearly forgotten that was a thing...
  - grp000 4y ago
    This was back when I was a student and had the FX and one GPUs. Getting an internship meant that I had the money for an upgrade, and the cheapest, most straightforward was to get a second GPU, or so I thought. Wasn't even that cheap because I had to put both the GPUs under water to keep them from overheating when both in the same PC.
louissan 4y ago
Anyone remember Pentium II and their new <del>sockets</del> cartridges? That didn't last long. Like what, one generation? Good. (saying that, but I remember purchasing a dual Pentium II motherboard for 2 400 MHz CPUs to speed up 3DStudio 4 renderings under Windows NT4... xD)
- scrlk 4y ago
  The reason why they went down the slot route was for packaging reasons. Cache was still external at that point. There would be performance benefits from brining it on die, but larger chips are more expensive to make & using two smaller dies (one for CPU & one for cache like the Pentium Pro) is still quite expensive. The middle ground was to put the CPU and cache on a single PCB, so you end up with a cartridge form factor. By the time the next generation rolled around it was possible to put the CPU and cache on the same die at a reasonable cost (Moore's law), making the cartridge form factor obsolete.
- LargoLasskhyfv 4y ago
  Ze Fuji Quicksnap CPUs. (Single use analog pocket cameras)
  - mardifoufs 4y ago
    Anymore details on those? I can't find any info on the CPUs inside
    - LargoLasskhyfv 4y ago
      It was an analogy. Because of the formfactor, which was very similar at the times. Fuji still makes things labeled as quicksnap for the same purpose, but they look very different now.
- pram 4y ago
  Pretty sure there was a slot Pentium 3. I thought it was cool at the time, made me think of a NES cartridge.
- 4y ago
cwilkes 4y ago
I wondered what happened to the head of Cyrix, Jerry Rogers. He died 2 years ago: https://obits.dallasnews.com/us/obituaries/dallasmorningnews/name/gerald-rogers-obituary?id=2227283 https://obits.dallasnews.com/us/obituaries/dallasmorningnews...
rondrabkin 4y ago
OK then, I was very heavily involved in both the item in the Intro (the flaw in the first Pentium, I was the production control guy in the sole source factory) and #1 on the list (Itanium, I was trying to get hardware companies to work with their software suppliers to port to the new architecture using a very significant budget). The common thread was Intel marketing pushing something that was a dog for marketing reasons 1. It is very amazing not in a good way when you think you have enough inventory but someone from HQ calls up the warehouse and has the older CPUs crushed by a bulldozer (you don't want to throw them out, they are quite usable) 2. Was amazing that sucker ran so hot tech support got a call about test boxes catching on fire
hilbert42 4y ago
"Note: Plenty of people will bring up the Pentium FDIV bug here, but the reason we didn’t include it is simple: Despite being an enormous marketing failure for Intel and a huge expense, the actual bug was tiny." The fact that the fault was tiny and that few people were affected is definatly NOT the point. The so-called Pentium 'bug' was the result of fundamentally terrible engineering on Intel's part in that the underlying design wasn't fit for purpose - it wasn't just a bug. It seems to me the authors of this story do not understand the implications of what Intel did was fundamentally wrong in that its math processing was flawed by design from the outset or otherwise they would have included the Pentium in their list. In order to achieve increased math processing speed, Intel broke mathematics algorithms down into part algorithm and part lookup tables - that is instead of having mathematics algorithms complete the whole task (which is the logical way of doing things). If the mathematics algorithm were wrong then every calculation would also be wrong and thus the problem obvious from the outset. Adding a lookup table makes calculations faster but one would then have had to test every combination in the lookup table - and Intel didn't. Look at the problem like this - think of a set of log or trig tables, now think of the implications if one of those table entries is incorrect. What Intel did was deliberate cheating and it failed to get away with it. Intel would have known this from the outset and thus the problem was an integral design fault rather than a bug. Intel knowingly implemented a design that had flawed data integrity at its most fundamental level. What Intel did was so nasty that it's hard to think of how it could have made matters worse than if it had deliberately tried to introduce a fault. In my opinion, any company that would stoop to such low ethical tactics as Intel did with the Pentium's design would have demonstrated that it cannot be trusted - and I've never trusted Intel from that point onward. If anyone ever needs a reason for why processors should have open design architectures that are subject to third-party scrutiny then this is the quintessential example.
- colejohnson66 4y ago
  > In order to achieve increased math processing speed, Intel broke mathematics algorithms down into part algorithm and part lookup tables - that is instead of having mathematics algorithms complete the whole task (which is the logical way of doing things). Can you expand on this? I thought all FPUs used lookup tables? Even the 8087 had them.
drallison 4y ago
Of course, what constitutes "worst" is a difficult question. Signetics made the 2650, a nice processor with a highly regular architecture with a condition code register. After every arithmetic operation including loads and stores the ALU updated the condition code register. The National 32032 processor was a wonderful part with a clarity of design that made it a great choice for a workhorse processor. Unix running the machine was stable and efficient except that every few weeks there would be disastrous crash. With a tremendous amount of effort the source of the problem was found: a race condition in the interrupt control logic that returned from the wrong stack and scribbled over memory. The Intel i860 exposed the internal computational pipeline to the programmer. Context switching was complicated by the conflict of real-time operating performance requirements and a deep pipeline with no way to grab the context and drain the pipeline. Eventually a dedicated team got a Unix OS running on the part, but it peformed poorly. The Maspar MP-1 was a SIMD machine. It was cool to test new library functions by seeing if, say, sqrt(x)*sqrt(x)==x for all floating point numbers. Customers wanted the Maspar machine to be timeshared, but the architecture made it difficult to do since the CPU state was very large and memory was not mapped. Intel's 8048 (and simplified versions like the 8021 and enhanced versions like the 8051) did not perform as well in terms of speed or code size as many of the competing micro controllers. The competition offered very simple asymmetric complex architectures which could be programmed (possibly with external hardware assists) to accomplish embedded tasks with significant effort and several days or weeks of effort. The Intel part was not quite as efficient in memory use and speed, but could be programmed in an afternoon. And another engineer/programmer could look at the code and understand it without much deep thought. The Motorola 68000 was a wonderful machine with a clear instruction set. But the original 68000 could not support virtual memory. There have been all sorts of different architectures tried which seen strange today but came about because the architecture was thought to provide an engineering solution to an immediate problem. There was a time when register machines were thought to be a bad architecture, far inferior to a simple stack architecture.

88 points by fzliu 4y ago

My first PC had a cyrix 333Mhz CPU. Ran just fine! But I was learning c in Borland turbo c and djgpp so it didn't have to do much. Running java on it... Well that wasn't fun with the 32MB RAM. Worked on itanium too. It was more amazing Microsoft actually had support for it.

velcrovan 4y ago

CTRL+F "transmeta crusoe": Not found ah well

mrintellectual 4y ago
My vote for worst CPU goes to the iAPX 432 (also not on this list).
- Max-q 4y ago
  When I saw the headline I expected the iAPX to be number one on the list.
- sidewndr46 4y ago
  I was looking for this as well. It should be on there for introducing a completely new architecture, costing more, and underperforming contemporary products from Intel's catalog.
- jandrese 4y ago
  Wow, a garbage collector implemented inside of the processor. Chip level support for objects. You can't fault Intel for their ambition here, just their common sense. And the whole thing is built for a world where everybody is writing code in Ada. I bet some compiler makers were salivating at the prospect of collecting all of those huge license fees from developers.
  - Taniwha 4y ago
    It was a different time - memory/CPU speed trade-offs were very different - we saw RISC once we were able to move cache on-chip (or very very close) - but at that point CISC made sense and the 432 pushed CISC to the extreme. IMHO the x86 won out (an d is still with us) because of all the CISCs of its time it was the closest to RISC when memory started to get a lot faster (almost all instructions make at most 1 memory access, few esoteric memory operations etc)
    - Thetawaves 4y ago
      All instructions take at least 1 memory access. All instructions that do memory access need at least 2 memory accesses.
  - p_l 4y ago
    I once encountered a note from one of the people working on iAPX 432, claiming that the core idea of high level cpu wasn't really the issue it tanked, but project mismanagement and horrible design applied which resulted in a chip that would be technologically at home... In 1960s, just done in VLSI - one of the things I recall were issues with actual physical implementation of the memory data paths resulting in horrible IPC
- ncmncm 4y ago
  Isn't the i860 the inheritor of iAPX 432 design details?
UmbertoNoEco 4y ago
Oh those were the days were I was young and naive and I thought Linus was going to change the world (again) blurring the lines between 'software' and 'hardware'
hajile 4y ago
I think transmeta was MUCH better than Itanium. Itanium held the idea that we could accurately predict ILP at compile time (when the halting problem clearly states that we cannot). Transmeta said VLIW has the best theoretical PPA possible, so let's wrap that in a large, programmable JIT to analyze/optimize stuff to take advantage. Modern CPUs run quite a bit closer to transmeta, but they largely use fixed-function hardware rather than being able to improve performance at a later time. If we could nail down that ideal VLIW architecture, we could sell a given chip at various process sizes and then offer various paid "software" upgrades or compatibility packs for various ISAs to run legacy code. At least there's a pipe dream worth looking into.
- cogman10 4y ago
  > Itanium held the idea that we could accurately predict ILP at compile time (when the halting problem clearly states that we cannot). I don't know where these notions are coming from. Compilers can (and do) reorder instructions to extract as much parallelism as possible. Further, SIMD has forced most compilers down a path of figuring out how to parallelize, at the instruction level, the processing of data. Further, most CPUs now-a-days are doing instruction reordering to try and extract as much instruction level parallelism out as possible. Figuring out what instructions can be run in parallel is a data dependency problem, one that compilers have been solving for years. Side note: the instruction reordering actually poses a problem for parallel code. Language writers and compiler writers have to be extra careful about putting up "fences" to make sure a read or write isn't happening outside a critical section when it shouldn't be.
  - p_l 4y ago
    The critical difference is that EPIC (the architecture model of Itanium) essentially exposed CPU pipelines naked to the code - so you didn't just have to reorder instructions as optimizers do today, you also had to figure out changes that experience so far suggests is doable either in hw with runtime-only data, or in very tight numerical code. This includes compiler taking the place of branch predictor as well as OOOE scheduling, as well as no on-cpu instruction reordering or out of order retirement, and IIRC a branch mispredict was quite costly. More over, EPIC pretty much meant thar you couldn't apply similar chip-level IPC improvements as you could elsewhere, at least originally.
deleted 4y ago
[deleted]
pengaru 4y ago
I had a Transmeta Crusoe based PC104 SBC and for the time it was relatively quick for something low power, does it really deserve to be in the "worst cpus ever" list? why for?
- velcrovan 4y ago
  You’re right. I was kind of being snarky. But it was a huge disappointment compared against the promises from Transmeta and the tech journalism of the time.

nesarkvechnep 4y ago

Cyrix wasn't the first company to build SoC, Acorn was.

fanf2 4y ago
You are referring to the ARM 250 chip in the Acorn A3010, A3020, and A4000 https://en.wikipedia.org/wiki/Acorn_Archimedes https://en.wikipedia.org/wiki/Acorn_Archimedes
- nesarkvechnep 4y ago
  Yes, thank you!

masklinn 4y ago

The lack of Alpha seems odd, though maybe that should be the worst ISA rather than merely individual CPU?

pinewurst 4y ago
Why would Alpha be the worst? I’ve owned 2 of them, 21064 and 21264, and they were fast and reliable.
- als0 4y ago
  The influence of Alpha on modern instruction sets like ARM64 and RISC-V is tremendous. It’s just sad it had to die for this to happen.
  - scrlk 4y ago
    I'd also add that a lot of excellent ex-Alpha engineers (e.g. Jim Keller, Dan Dobberpuhl off the top of my head) ended up designing great chips at other companies.
  - hajile 4y ago
    It didn't die. Intel bought it from HP, stripped it for parts, then killed it. HyperTransport and a few other things were essentially just copies of Alpha's stuff cleanroom implemented by ex-Alpha employees. Designs like Sandy Bridge look quite similar to EV8. QuickPath is just Alpha's interconnect with some updates (HyperTransport was also a cleanroom copy from ex-Alpha employees). Even AVX seems inspired by the 1048-bit SIMD planned for EV9/10.
  - jeffbee 4y ago
    How did the Alpha ISA influence RISC-V, other than by its counterexample? Does RISC-V lack an integer divide? "Design of the RISC-V Instruction Set Architecture" mainly uses Alpha in the phrase "Unlike Alpha, ..." i.e. as a warning to future people. In fact, the author fairly well excoriates all of the historic RISC architectures for being myopically designed.

xbar 4y ago

I'm so ashamed to have owned a Cyrix, a P4, and an AMD Bulldozer. They were all awful.

josteink 4y ago
I’ve had a P4 and I didn’t consider it “awful”. It was without a doubt the fastest CPU I had ever had at the time, but boy did it generate heat and need cooling. That machine sounded like a always on vacuum-cleaner.
- sidewndr46 4y ago
  I owned a Pentium 4 as well (oh boy did I save for a long time as a teenager to afford that). It wasn't really as bad as what this article claims. On the other hand, the dual-core parts probably really are that bad.
  - jandrese 4y ago
    The article did call out in particular the late generation P4s with the super duper extra long pipeline that simply couldn't keep themselves fed when working with anything but synthetic benchmarks.
zepearl 4y ago
Intel was too expensive for me, so I ended up buying a Cyrix => performance (floating point) was terrible in Falcon 3, I was sooo sad - but on the other hand that gave me until today the push to really focus on details before taking a decision => thank you Cyrix for having changed my life hehe.
pseudosavant 4y ago
I had two Bulldozers. Bulldozer wasn't competitive at the top end, but I always found Athlon chips to be cheaper than their performance equivalent Intel part. So the fastest AMD chip would be cheaper than the third fastest Intel part. Still a good value. Terrible for AMD's bottom-line though.

hajile 4y ago

This doesn't seem to be the best-researched article out there. If they thought Itanium was bad, they should have looked into the i860. Itanium was an attempt to fix a bunch of the i860 ideas. i860 quickly went from a supercomputer chip to a cheap DSP alternative (where it had at least the hope of hitting more than 10% of its theoretical performance). Intel iAPX 432 was preached as the second coming back in the 80s, but failed spectacularly. The i960 was take 2 and their joint venture called BiiN also shuttered. Maybe Rekursiv would be worthy of a mention here too. We now know that core 2 dropped all kinds of safety features resulting in the Meltdown vulnerabilities. It also partially explains why AMD couldn't keep up as these shortcuts gave a big advantage (though security papers at the time predicted that meltdown-style attacks existed due to the changes). Rather than an "honorable mention", the Cell processor should have easily topped the list of designs they mentioned. It was terrible in the PS3 (with few games if any able to make full use of it) and it was terrible in the couple supercomputers that got stuck with it. I'd also note that Bulldozer is also maligned more than it should be. There's a lot to like about the concept of CMT and for the price, they weren't the worst. I'd even go so far as to say that if AMD wasn't so starved for R&D money during that period, they may have been able to make it work. ARM's latest A510 shares more than a few similarities. A big/little or big/little/little CMT architecture seems like a very interesting approach to explore in the future.

causality0 4y ago
Yes, and no mention of the Transmeta Crusoe either.
the_only_law 4y ago
> The i960 was take 2 and their joint venture called BiiN also shuttered. I have an old X-11 terminal I believe has a i960 in it. I’m shocked that thing was capable of running CDE desktops when it stutters on FVWM over a network much faster than it ever was intended to see.
notacoward 4y ago
At least the 960 was somewhat usable. Many variants were created, and several were widely used in embedded products for quite a few years. The 860, however, was Just Crap. Full stop. End of story. IIRC it had weird double-instruction modes that compilers just couldn't handle, and if you used them anyway (for very necessary performance) then handling exceptions properly was all but impossible. Definitely gets my vote for worst ever.

SeanLuke 4y ago

What does "worst CPU" mean? I think that it means, regardless of market success, the CPU that most hindered, indeed retarded, progress in CPU engineering history. In this regard, #1 and #2 are clearly the 8088 and 80286 respectively.

als0 4y ago
Agreed. I think Itanium gets a lot of unnecessary slack. It really tried some exciting new ideas and clean concepts. Not all of those concepts were much of a win, but with the first chip arriving years late then there’s no wonder it was perceived as underwhelming from the get go (that would happen to any chip that’s late)
- cogman10 4y ago
  Funnily, I feel like SIMD instructions are slowly reinventing what the itanium did out of the box. I think a modern compiler could likely do a good job with itanium now-a-days. However, when it first came out, there simply wasn't the ability to keep those instruction batches full. Compiler tech was too far behind to work well with the hardware.
  - zamadatix 4y ago
    I'm not sure I'd say many compilers are even that great with SIMD these days and that is easier than what the itanium was asking of compilers. There are real gains to be had by using SIMD but it tends to be massively parallel data processing workloads with specially written SIMD code or even hand tuned assembly (image/video processing, neural networks) not just feeding in a source file and compiling with the SIMD flag to then realize meaningful gains.
    - cogman10 4y ago
      The reverse is true. SIMD is harder because you have to have a uniform operation across a set of data. Imagine a for loop that looks like this int[] x, y, z; int[] p, d, q; for (int i = 0; i < size; ++i) { p[i] = x[i] / z[i] d[i] = z[i] * x[i] q[i] = y[i] + z[i] } For SIMD, this is a complicated mess for the compiler to unravel. What the compiler would LIKE to do is turn this into 3 for loops and use the SIMD instructions to perform those operations in parallel. The itanium optimization, however, is a lot easier. The compiler can see that none of p, d, or q depend on the results of the previous stage (that is q[i] doesn't depend on p[i]). As a result, the entire thing can be packed into a single operation. Now, of course, modern OOO processors can do the same optimization so maybe it's not a huge win? Still, would have been something worth exploring more (IMO) but the market forces killed it. Moving that sort of optimization out of the processor hardware and into the compiler software seems like it could lead to some nice power/performance benefits.

tangental 4y ago

I visted this page hoping to see the PowerPC 970 top of the list, but all it gets is a "Dishonorable Mention". After going through three PowerMac G5s, all of which had their processors die within 4 years, I still bear a grudge.

sidewndr46 4y ago
For us non Apple users, how is that possible? I don't think I've ever had a CPU die other than by lightning.
- kzrdude 4y ago
  I was imagining lightning struck the cpu specifically, leaving the rest intact? Quite the precision.
  - sidewndr46 4y ago
    Oh no, the last time this happened there were definitely other casualties. The motherboard was left in a particular state of undeath, where it wouldn't quite power on. But if you jumped the ATX header it'd sort of attempt to boot and give some beeps. After that I added a bunch of grounding to my house and I haven't had that much damage in one lightning strike before.
- giantrobot 4y ago
  I don't know what OP was running but the G5 iMacs were some of the machines suffering from the early 2000s capacitor plague[0]. The power supplies and power regulation on the logic boards would die on those all the time. If you were lucky it was just the power supply but the problem usually needed a PSU and logic board swap. [0] https://www.cnet.com/culture/pcs-plagued-by-bad-capacitors/ https://www.cnet.com/culture/pcs-plagued-by-bad-capacitors/
- pram 4y ago
  The processor in a G5 PowerMac came on a card that had the VRMs, capacitors, and a bunch of other stuff on it. It was basically like a tiny motherboard that attached to your motherboard.

annoyingnoob 4y ago

I've owned 4 or 5 of the CPUs on that list over the years. I'm sure there are worse.

McGlockenshire 4y ago

I'm currently building a homebrew system built on the TMS99105A CPU, one of the final descendants of the TMS9900. It's a nifty little CPU. There's a lot of hidden little features once you dig in. It can actually address multiple separate 64k memory namespaces: data memory, instruction memory, macroinstruction memory, and mapped memory with the assistance of a then-standard chip. Normally these are all the same space and just need external logic to differentiate them. There's also a completely separate serial and parallel hardware interface bus. The macroinstruction ("Macrostore") feature is pretty fun. There's sets of opcodes that will decode into illegal instructions that, instead of immediately erroring out, will go looking for a PC and workspace pointer (the "registers") in memory and jump there. Their commercial systems like the 990/12 used this feature to add floating point and other features like stack operations. Yup, there's no stack. Just the 16 "registers," which live in main memory. There are specific branch and return instructions that store the previous PC and register pointer in the top registers of the new "workspace," allowing you direct access to the context of the caller. The assembly language is simple and straightforward with few surprises, but it's also clearly an abstraction over the underlying mechanisms of the CPU. I believe this then classifies this CPU as CISC incarnate. There are some brilliant and insane people on the Atari Age forums! One of them managed to extract and post the data for a subset of those floating point instructions, and then broke it all down and how it all worked. Some are building new generations of previous TMS9900 systems. One of them is replicating the CPU in an FPGA. A few others are building things like a full-featured text editor and, of course, an operating system. I've learned a hell of a lot during this project. I've been documenting what I'm doing and am planning to eventually make it into a pretty build log. I think this is a beautiful dead platform that deserved better.

ncmncm 4y ago
The TI's serial I/O bus takes the prize, for me.
throwawayboise 4y ago
I have a soft spot for that CPU. My first computer was a TI99/4a when I was about 14 or 15. I started with BASIC, then learned assembly language on that machine. I give it a lot of credit for starting the trajectory my future took.

alkaloid 4y ago

As a system builder for a "custom computer shop" back in 1997/98, I came here just to make sure Cyrix was on the list.

gattilorenz 4y ago
No IDT WinChip though, that's mildly surprising
- timw4mail 4y ago
  I don't think the Winchip was that well known. But it never pretended to be a high performing design.
  - gattilorenz 4y ago
    The list includes the MediaGX, so I thought it might be comparable in popularity/performance expectations. To be honest, I remember the WinChip because I thought the printed Windows logo on the CPU was pretty cool. Texas and AMD also had the "designed for Windows 95" logo on some of their CPUs (some 486 and Overdrive designs, iirc)

bstar77 4y ago

I would vote for the Pentium IV for all the reasons mentioned in the article, but more importantly because it was initially coupled with Rambus memory. Intel pushed that tech so hard to try and squeeze out AMD. Super high frequency, high bandwidth, high expense memory with terrible latency was not the future anyone wanted. Intel's hubris back then was off the charts. I know intel wanted Itanium to succeed for the same reasons, but the PIV came very close to home since it actually shipped for consumers. Oddly enough, Extreme Tech was a huge shill for Intel back in those days. Funny they don't mention that in this article.

StillBored 4y ago

Man, that 6x86 CPU is still getting the short end of the stick nearly three decades later despite being a pretty solid chip. So, first it generally had a higher IPC than anything else available (ignoring the P6). So, the smart marketing people at cyrix decided they were going to sell it based on a PR rating which was the average performance on a number of benchmarks vs a similar pentium. AKA a Cyrix PR166 (clocked at 133Mhz) was roughly the same perf as a 166Mhz pentium. Now had they actually been selling it for a MSRP similar to a pentium 166 that might have seemed a bit shady, but they were selling it closer to the price of a pentium 75/90. Then along comes quake which is hand optimized for the pentium's U/V pipeline architecture and happens to use floating point too. And since a number of people had pointed out the Cx86's floating point perf was closer in "PR" ratings to its actual clock speed suddenly you have a chip performing at much less than its PR rating, and certain people then proceeded to bring up the fact that it was more like a 90Mhz pentium in quake than a 166Mhz pentium (something i'm sure made, say intel, really happy) at every chance they get. So, yah here we are 20 years later putting a chip with what was generally a higher IPC than its competitors on a "shit" list mostly because of one benchmark. While hopefully all being aware that these shenanigins continue to this day, a certain company will be more than happy to cherry pick a benchmark and talk up their product while ignoring all the benchmarks that make it look worse. Now as far as motherboard compatibility, that was true to a certain extent if you didn't bother to assure your motherboard was certified for the higher bus rates required by the cyrix, and the other being it tended to require more sustained current than the intels the motherboards were initially designed for. So, yah the large print said "compatible with socket7" the fine print later added that they needed to be qualified, and the whole thing paved the way for the super socket7 specs which AMD made use of. And of course lots of people didn't put large enough heatsink/fans on them which they needed to be stable. So, people are shitting on a product that gets a bad rep because they were mostly ignorant of what we have all come to accept as normal business when your talking about differing micro architectural implementations. PS: Proud owner of a 6x86 that cost me about the same as a pentium 75, and not once do I think it actually performed worse than that, while for the most part (compiling code, and running everything else including Unreal) it was significantly better than my roommates pentium75.

hulitu 4y ago

scrlk 4y ago

A different twist on the Itanium: technically bad but ended up as a strategic win for Intel. SGI, Compaq and HP mothballed development of their own CPUs (MIPS/Alpha/PA-RISC) as they all settled on Itanium for future products. After Itanium turned out to be a flop, those companies adopted x86-64 - Intel killed off 3 competing ISAs by shipping a bad product.

Melatonic 4y ago
Interesting take!
sanguy 4y ago
Very true, it was the end of the DEC Alpha as Compaq chose the Itanic.
npunt 4y ago
Itanium was the OS/2 of chips, Microsoft used OS/2 to get IBM chasing a dead end while they baked Windows NT & 95 until their lead was secured.

grp000 4y ago

For a bit of time, I ran an over clocked FX 8320 and crossfire 7970's. The heat that machine put out was tremendous. I only had a wall mounted AC unit so I had to practically take my shirt off when I loaded it up.

robotnikman 4y ago
Ah yes, AMD/ATI crossfire. I had nearly forgotten that was a thing...
- grp000 4y ago
  This was back when I was a student and had the FX and one GPUs. Getting an internship meant that I had the money for an upgrade, and the cheapest, most straightforward was to get a second GPU, or so I thought. Wasn't even that cheap because I had to put both the GPUs under water to keep them from overheating when both in the same PC.

louissan 4y ago

Anyone remember Pentium II and their new <del>sockets</del> cartridges? That didn't last long. Like what, one generation? Good. (saying that, but I remember purchasing a dual Pentium II motherboard for 2 400 MHz CPUs to speed up 3DStudio 4 renderings under Windows NT4... xD)

scrlk 4y ago
The reason why they went down the slot route was for packaging reasons. Cache was still external at that point. There would be performance benefits from brining it on die, but larger chips are more expensive to make & using two smaller dies (one for CPU & one for cache like the Pentium Pro) is still quite expensive. The middle ground was to put the CPU and cache on a single PCB, so you end up with a cartridge form factor. By the time the next generation rolled around it was possible to put the CPU and cache on the same die at a reasonable cost (Moore's law), making the cartridge form factor obsolete.
LargoLasskhyfv 4y ago
Ze Fuji Quicksnap CPUs. (Single use analog pocket cameras)
- mardifoufs 4y ago
  Anymore details on those? I can't find any info on the CPUs inside
  - LargoLasskhyfv 4y ago
    It was an analogy. Because of the formfactor, which was very similar at the times. Fuji still makes things labeled as quicksnap for the same purpose, but they look very different now.
pram 4y ago
Pretty sure there was a slot Pentium 3. I thought it was cool at the time, made me think of a NES cartridge.
4y ago

cwilkes 4y ago

I wondered what happened to the head of Cyrix, Jerry Rogers. He died 2 years ago: https://obits.dallasnews.com/us/obituaries/dallasmorningnews/name/gerald-rogers-obituary?id=2227283 https://obits.dallasnews.com/us/obituaries/dallasmorningnews...

rondrabkin 4y ago

OK then, I was very heavily involved in both the item in the Intro (the flaw in the first Pentium, I was the production control guy in the sole source factory) and #1 on the list (Itanium, I was trying to get hardware companies to work with their software suppliers to port to the new architecture using a very significant budget). The common thread was Intel marketing pushing something that was a dog for marketing reasons 1. It is very amazing not in a good way when you think you have enough inventory but someone from HQ calls up the warehouse and has the older CPUs crushed by a bulldozer (you don't want to throw them out, they are quite usable) 2. Was amazing that sucker ran so hot tech support got a call about test boxes catching on fire

hilbert42 4y ago

"Note: Plenty of people will bring up the Pentium FDIV bug here, but the reason we didn’t include it is simple: Despite being an enormous marketing failure for Intel and a huge expense, the actual bug was tiny." The fact that the fault was tiny and that few people were affected is definatly NOT the point. The so-called Pentium 'bug' was the result of fundamentally terrible engineering on Intel's part in that the underlying design wasn't fit for purpose - it wasn't just a bug. It seems to me the authors of this story do not understand the implications of what Intel did was fundamentally wrong in that its math processing was flawed by design from the outset or otherwise they would have included the Pentium in their list. In order to achieve increased math processing speed, Intel broke mathematics algorithms down into part algorithm and part lookup tables - that is instead of having mathematics algorithms complete the whole task (which is the logical way of doing things). If the mathematics algorithm were wrong then every calculation would also be wrong and thus the problem obvious from the outset. Adding a lookup table makes calculations faster but one would then have had to test every combination in the lookup table - and Intel didn't. Look at the problem like this - think of a set of log or trig tables, now think of the implications if one of those table entries is incorrect. What Intel did was deliberate cheating and it failed to get away with it. Intel would have known this from the outset and thus the problem was an integral design fault rather than a bug. Intel knowingly implemented a design that had flawed data integrity at its most fundamental level. What Intel did was so nasty that it's hard to think of how it could have made matters worse than if it had deliberately tried to introduce a fault. In my opinion, any company that would stoop to such low ethical tactics as Intel did with the Pentium's design would have demonstrated that it cannot be trusted - and I've never trusted Intel from that point onward. If anyone ever needs a reason for why processors should have open design architectures that are subject to third-party scrutiny then this is the quintessential example.

colejohnson66 4y ago
> In order to achieve increased math processing speed, Intel broke mathematics algorithms down into part algorithm and part lookup tables - that is instead of having mathematics algorithms complete the whole task (which is the logical way of doing things). Can you expand on this? I thought all FPUs used lookup tables? Even the 8087 had them.

drallison 4y ago

Of course, what constitutes "worst" is a difficult question. Signetics made the 2650, a nice processor with a highly regular architecture with a condition code register. After every arithmetic operation including loads and stores the ALU updated the condition code register. The National 32032 processor was a wonderful part with a clarity of design that made it a great choice for a workhorse processor. Unix running the machine was stable and efficient except that every few weeks there would be disastrous crash. With a tremendous amount of effort the source of the problem was found: a race condition in the interrupt control logic that returned from the wrong stack and scribbled over memory. The Intel i860 exposed the internal computational pipeline to the programmer. Context switching was complicated by the conflict of real-time operating performance requirements and a deep pipeline with no way to grab the context and drain the pipeline. Eventually a dedicated team got a Unix OS running on the part, but it peformed poorly. The Maspar MP-1 was a SIMD machine. It was cool to test new library functions by seeing if, say, sqrt(x)*sqrt(x)==x for all floating point numbers. Customers wanted the Maspar machine to be timeshared, but the architecture made it difficult to do since the CPU state was very large and memory was not mapped. Intel's 8048 (and simplified versions like the 8021 and enhanced versions like the 8051) did not perform as well in terms of speed or code size as many of the competing micro controllers. The competition offered very simple asymmetric complex architectures which could be programmed (possibly with external hardware assists) to accomplish embedded tasks with significant effort and several days or weeks of effort. The Intel part was not quite as efficient in memory use and speed, but could be programmed in an afternoon. And another engineer/programmer could look at the code and understand it without much deep thought. The Motorola 68000 was a wonderful machine with a clear instruction set. But the original 68000 could not support virtual memory. There have been all sorts of different architectures tried which seen strange today but came about because the architecture was thought to provide an engineering solution to an immediate problem. There was a time when register machines were thought to be a bad architecture, far inferior to a simple stack architecture.