9 ms·

As someone who doesn't follow RISC-V too closely, how does the most modern one (either available or planned) stack up in terms of perf compared to x86/arm? Just

As someone who doesn't follow RISC-V too closely, how does the most modern one (either available or planned) stack up in terms of perf compared to x86/arm? Just curious when these will begin to become viable for consumer devices. Years? Decades?

deleted 4y ago
[deleted]
mhh__ 4y ago
In terms of current chips they're the best part of a decade away. You can't buy a RISC-V processor competitive with a good arm chip let alone an X86 or a really good arm chip like M1 Current cores, however, are fairly competitive in terms of perf per MHz, but this has to be taken with a grain of salt because the proof is in the taste not the ingredients.
socialdemocrat 4y ago
RISC-V cores are about 4 years behind ARM. So most they are most suitable for embedded systems and single board computers at the moment. At the lower end they have a big advantage as they can reach similar performance as Arm at half the silicon which translates into 4x lower price at similar volume of production. But for high-end chips you will not see this difference. SiFive has caught up about 2 years each year. So I suspect it will not work 3-4 years before RISC-V can compete with Arm desktop computers. Competing with Apple will take much longer. But such perspectives kind of miss the point. Then beauty of RISC-V is that it can be used in all sorts of specialized hardware such as accelerators. You may be able to program AI engines or maybe even some kind of graphics card with RISC-V instructions in the future.
- zozbot234 4y ago
  If anything, a more streamlined frontend matters more at the high-end, because it enables more scalable decode letting you extract increased parallelism out of the code. Better use of your frontend complexity budget also makes it easier to use things like fused microinsn sequences, or the RISC-V compressed insn set which brings code density on par with x86 (an outstanding result for such a clean design) for both RV32 and RV64. This is pretty much what we see going from x86 to ARM, and RISC-V only goes further in the same direction.
  - seoaeu 4y ago
    Decode doesn't take up much space in a high-end processor. Even if your architecture's decoder doesn't "scale" as well, you can just throw a bunch more transistors at it to get performance. That said, I doubt there's many CPU designers unhappy about a simpler ISA...
    - imtringued 4y ago
      If macro op fusion is viable then there are more opportunities to throw more transistors at it to get more performance.
      - saagarjha 4y ago
        It's not yet clear if macro-op fusion will really be a thing.
        kragen 4y ago
        Hmm, I'm no expert on the subject, but I had heard that CMP/Jcc and TEST/Jcc macro-op fusion has been critical to i386 and amd64 performance, for both Intel and AMD processors, for about 15 years?
        saagarjha 4y ago
        Those are "simple" fusions that processor do perform productively. The thing with RISC-V is that a lot of the design rides on "oh we're just going to combine all the very RISC instructions into macro-ops to catch up to what ARM is doing" except nobody is really doing that kind of fusion right now, so it's not clear if this is even feasible.
        kragen 4y ago
        Hmm, not even the Allwinner D1 or the SiFive P650? In https://news.ycombinator.com/item?id=29423006 https://news.ycombinator.com/item?id=29423006 Bruce Hoult says SiFive has been doing macro-op fusion in one case since the 7-series, and I think he's the one that implemented it. In https://news.ycombinator.com/item?id=29444322 https://news.ycombinator.com/item?id=29444322 "ruslan" links the original macro-op fusion stuff from 02016: https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fusion-finalV2.pdf https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fu... and https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318. Surprisingly, those present "shootout" results that are really just "effective dynamic instruction" counts and "dynamic byte" counts, ending in a "design proposal"; they don't seem to have simulated macro-op fusion at RTL level, much less in an FPGA or a MOSIS run.
duskwuff 4y ago
All of the commercially available RISC-V processors I'm aware of are microcontrollers -- they're competing with ARM Cortex-M. They're still a ways off from anything that can compete with ARM Cortex-A application processors or Intel/AMD desktop/laptop CPUs.
- beebeepka 4y ago
  Not just controllers. There are several commercially available single board computers running Linux. Check out the "explaining computers" YouTube channel for at least a couple fairly recent board reviews. They are slow but do exist
seoaeu 4y ago
Many billions of RISC-V of CPUs have shipped, so, pedantically, that means they're already viable for including inside consumer devices. However as other replies have noted, you'll have to wait a number of years before they'll be used as the main CPU, rather than just some tiny core off on the side doing power management or whatever.

deleted 4y ago

[deleted]

mhh__ 4y ago

In terms of current chips they're the best part of a decade away. You can't buy a RISC-V processor competitive with a good arm chip let alone an X86 or a really good arm chip like M1 Current cores, however, are fairly competitive in terms of perf per MHz, but this has to be taken with a grain of salt because the proof is in the taste not the ingredients.

socialdemocrat 4y ago

RISC-V cores are about 4 years behind ARM. So most they are most suitable for embedded systems and single board computers at the moment. At the lower end they have a big advantage as they can reach similar performance as Arm at half the silicon which translates into 4x lower price at similar volume of production. But for high-end chips you will not see this difference. SiFive has caught up about 2 years each year. So I suspect it will not work 3-4 years before RISC-V can compete with Arm desktop computers. Competing with Apple will take much longer. But such perspectives kind of miss the point. Then beauty of RISC-V is that it can be used in all sorts of specialized hardware such as accelerators. You may be able to program AI engines or maybe even some kind of graphics card with RISC-V instructions in the future.

zozbot234 4y ago
If anything, a more streamlined frontend matters more at the high-end, because it enables more scalable decode letting you extract increased parallelism out of the code. Better use of your frontend complexity budget also makes it easier to use things like fused microinsn sequences, or the RISC-V compressed insn set which brings code density on par with x86 (an outstanding result for such a clean design) for both RV32 and RV64. This is pretty much what we see going from x86 to ARM, and RISC-V only goes further in the same direction.
- seoaeu 4y ago
  Decode doesn't take up much space in a high-end processor. Even if your architecture's decoder doesn't "scale" as well, you can just throw a bunch more transistors at it to get performance. That said, I doubt there's many CPU designers unhappy about a simpler ISA...
  - imtringued 4y ago
    If macro op fusion is viable then there are more opportunities to throw more transistors at it to get more performance.
    - saagarjha 4y ago
      It's not yet clear if macro-op fusion will really be a thing.
      - kragen 4y ago
        Hmm, I'm no expert on the subject, but I had heard that CMP/Jcc and TEST/Jcc macro-op fusion has been critical to i386 and amd64 performance, for both Intel and AMD processors, for about 15 years?
        saagarjha 4y ago
        Those are "simple" fusions that processor do perform productively. The thing with RISC-V is that a lot of the design rides on "oh we're just going to combine all the very RISC instructions into macro-ops to catch up to what ARM is doing" except nobody is really doing that kind of fusion right now, so it's not clear if this is even feasible.
        kragen 4y ago
        Hmm, not even the Allwinner D1 or the SiFive P650? In https://news.ycombinator.com/item?id=29423006 https://news.ycombinator.com/item?id=29423006 Bruce Hoult says SiFive has been doing macro-op fusion in one case since the 7-series, and I think he's the one that implemented it. In https://news.ycombinator.com/item?id=29444322 https://news.ycombinator.com/item?id=29444322 "ruslan" links the original macro-op fusion stuff from 02016: https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fusion-finalV2.pdf https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fu... and https://arxiv.org/abs/1607.02318 https://arxiv.org/abs/1607.02318. Surprisingly, those present "shootout" results that are really just "effective dynamic instruction" counts and "dynamic byte" counts, ending in a "design proposal"; they don't seem to have simulated macro-op fusion at RTL level, much less in an FPGA or a MOSIS run.

duskwuff 4y ago

All of the commercially available RISC-V processors I'm aware of are microcontrollers -- they're competing with ARM Cortex-M. They're still a ways off from anything that can compete with ARM Cortex-A application processors or Intel/AMD desktop/laptop CPUs.

beebeepka 4y ago
Not just controllers. There are several commercially available single board computers running Linux. Check out the "explaining computers" YouTube channel for at least a couple fairly recent board reviews. They are slow but do exist

seoaeu 4y ago

Many billions of RISC-V of CPUs have shipped, so, pedantically, that means they're already viable for including inside consumer devices. However as other replies have noted, you'll have to wait a number of years before they'll be used as the main CPU, rather than just some tiny core off on the side doing power management or whatever.