Any idea when this was written? It seems a bit out dated, and I'm especially surprised at the mention of hardware companies not using linters, that seems insane

Any idea when this was written? It seems a bit out dated, and I'm especially surprised at the mention of hardware companies not using linters, that seems insane to me. Lint, Logic Equalivance, CDC, etc are all absolutely required sanity checks on hardware design, irrespective of the language. Also SystemVerilog is quite esperessive. I definitely agree Verilog has many pitfalls you basically get used to and know to avoid, but I don't agree that knowing in your head the hardware that will be generated is a bad thing. Knowing how the hardware will be constructed from your code is key to getting it running at 4Ghz instead of 100Mhz. What your code will infer could be less or more area efficient, etc. Modern synthesis tools do help map sometimes inefficient code to the right hardware, but still knowing what it should create is a positive thing.