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What does your benchmarking workflow look like? I am interested in * From a high level what does your dev iteration look like? * Getting instruction trace

What does your benchmarking workflow look like? I am interested in * From a high level what does your dev iteration look like? * Getting instruction traces, timing and resimulating those traces * Power analysis, timing analysis (do you do this as part of performance simulation) ? * Do you benchmark the whole chip or specific sub units? * How do you choose what to focus on in terms of performance enhancements? * What areas are you focusing on now? * What tools would make this easier?

Taniwha 5y ago
At the moment I'm just starting working my way up the hierarchy of benchmarks, dhrystone's been useful though it's nearing the end of its use - I build the big FPGA version (on an AWS FPGA instance) to give me a place to run bigger things exactly like this. I currently run low level simulations in Verilator where I can easily take large internal architectural trace, and bigger stuff on AWS (where that sort of trace is much much harder) I haven't got to the power analysis stage - that will need to wait until we decide to build a real chip - timing will depend on final tools if we get to build something real, currently it's building on Vivado for the FPGA target. Mostly I'm doing whole chip tests - getting everything to work well together is sort of the area I'm focusing on at the moment (correctness was the previous goal - being together enough to boot linux), the past 3 months I've brought the performance up b y a factor of 4 - the trace cache might get me 2x more if I'm lucky. I spend a lot of time looking at low level performance, at some level I want to get the IPC (instructions per clock) of the main pipe as high as I can so I stare at the spots where that doesn't happen I'm using open source tools (thanks everyone!)
- tromp 5y ago
  > dhrystone's been useful though it's nearing the end of its use Would my fhourstones [1] [2] benchmark be of any use? [1] https://tromp.github.io/c4/fhour.html https://tromp.github.io/c4/fhour.html [2] https://openbenchmarking.org/test/pts/fhourstones https://openbenchmarking.org/test/pts/fhourstones
  - Taniwha 5y ago
    thanks I'll have a look - I'm not so interested in raw scores, more about relative numbers so I can judge different architectural experiments
- deleted 5y ago
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Taniwha 5y ago

At the moment I'm just starting working my way up the hierarchy of benchmarks, dhrystone's been useful though it's nearing the end of its use - I build the big FPGA version (on an AWS FPGA instance) to give me a place to run bigger things exactly like this. I currently run low level simulations in Verilator where I can easily take large internal architectural trace, and bigger stuff on AWS (where that sort of trace is much much harder) I haven't got to the power analysis stage - that will need to wait until we decide to build a real chip - timing will depend on final tools if we get to build something real, currently it's building on Vivado for the FPGA target. Mostly I'm doing whole chip tests - getting everything to work well together is sort of the area I'm focusing on at the moment (correctness was the previous goal - being together enough to boot linux), the past 3 months I've brought the performance up b y a factor of 4 - the trace cache might get me 2x more if I'm lucky. I spend a lot of time looking at low level performance, at some level I want to get the IPC (instructions per clock) of the main pipe as high as I can so I stare at the spots where that doesn't happen I'm using open source tools (thanks everyone!)

tromp 5y ago
> dhrystone's been useful though it's nearing the end of its use Would my fhourstones [1] [2] benchmark be of any use? [1] https://tromp.github.io/c4/fhour.html https://tromp.github.io/c4/fhour.html [2] https://openbenchmarking.org/test/pts/fhourstones https://openbenchmarking.org/test/pts/fhourstones
- Taniwha 5y ago
  thanks I'll have a look - I'm not so interested in raw scores, more about relative numbers so I can judge different architectural experiments
deleted 5y ago
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