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No. Firstly -march (or similar, e.g. -mcpu in LLVM land) should target a chip not individual instruction sets. Secondly, AVX-512 alone has a handful of differe
by mhh__ 5y ago
No. Firstly -march (or similar, e.g. -mcpu in LLVM land) should target a chip not individual instruction sets.
Secondly, AVX-512 alone has a handful of different extensions. There are a bunch of different SSE variants, and similarly instructions are still being added to the VEX prefix (normal AVX).
There is more potentially for getting it wrong with riscv but 64 bit implies a number of extensions too so it's too far off what amd64 originally meant for X86 (e.g. implies SSE2)
- IshKebab 5y agoWhat do you mean "no"? My comment was entirely factual. > Firstly -march (or similar, e.g. -mcpu in LLVM land) should target a chip not individual instruction sets. LLVM still uses -march. And no you shouldn't target a specific chip unless you know your code will only run on that chip. That's the whole point I'm making. Sometimes you do know that (in embedded situations) but often you don't. Desktop apps aren't compiled for specific chips. > Secondly, AVX-512 alone has a handful of different extensions. Yes but these are generally linear - if an x86 chip supports extension N it will support extension N-1 too. Not true for RISC-V.
- mhh__ 5y agoThe LLVM tools (like llc) use -mcpu. Clang mimics GCC. My point about the specific chip is that you have to know it anyway if you're planning on targeting a combination of extensions so you might as well use it. As for linearity, the "generally" bit will apply to RISC-V by the time we have real desktop class chips using the ISA. We still can't assume AVX support for most programs, I don't view this as any different to RISC-V extensions. Just this ~year Intel added VEX-coded AI NN acceleration instructions, I assume RISC-V has similar plans.
- IshKebab 5y agoLLVM uses -march and -mcpu. It seems to be a bit of a mess which one you should use and also depend on the architecture. Time will tell if there's a de facto minimum set of extensions for desktop RISC-V. Let's hope so, but it isn't guaranteed.
- monocasa 5y ago> Yes but these are generally linear - if an x86 chip supports extension N it will support extension N-1 too. Not true for RISC-V. Not if you include AMD and Intel cores in that.
- IshKebab 5y agoWhy do you say that? Look here: https://clang.llvm.org/docs/UsersManual.html#x86 https://clang.llvm.org/docs/UsersManual.html#x86
- deleted 5y ago[deleted]
- monocasa 5y agoThat list isn't really an accurate picture of the world, but a vague attempt to make sense of the madness. There's plenty of cores that don't follow that versioning scheme, and it's not an Intel or AMD construct.