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FPGA with Multiple ISA?
Back in the dawn of time the machines I worked on had application-specific instruction set architectures. IBM made 'scientific' and 'business' computers. The 360 line converged these.
With microcoded architectures today it would be possible to dynamically load a custom application-specific instruction set into microcode from an FPGA. This could greatly increase the efficiency of certain kinds of computation. The FPGA can be dynamically updated with new microcode architectures.
For example, a lisp-machine architecture for running lisp code, a prolog machine architecture for prolog code handling backtracking, an APL architecture for array processing, a SQL architecture for databases, etc.
These instruction sets could be dynamically swapped. For example, the register bank could be configured to match a particular SQL table structure and manipulated with SQL-specific instructions. Register banks configured as content-addressable memory could greatly speed up table searches.
In particular, with RISC-V, one could define a special-case extension instruction set that could be 'swapped in' to the microcode, making it ideal for handling special purpose hardware like a GPU for bitcoins or a quantum computer instruction set handling unitary matrices.
I feel we've reached the limits of things a general purpose architecture can do.
Intel has an FPGA/CPU pair (which unfortunately I can't get because I'm not a huge corporation) but I don't think the FPGA/CPU can modify the CPU microcode. Perhaps they might hit on the idea with their marriage to the RISC-V community.
The ability to modify the data paths in a set of general purpose processor components (e.g. register banks, caches, integer ALU, float ALU, vector ALU, pipeline lookahead, etc) for specific applications by modifying the microcode would be a real leap forward.
- xodjmk 5y agoWhat you are describing is called an 'overlay'. Basically an overlay is some sort of computing architecture built with/on top of FPGA fabric. Soft processors are an example of overlay. You could imagine some kind of special linear algebra computing engine, etc. as other examples. RISC-V soft processors already exist. I'm pretty sure you could find some open source projects floating around. The trick is to make something that could actually out perform existing FPGA/CPU devices (SoC). Xilinx, now AMD, makes quite affordable Zynq Ultrascale devices that have FPGA+ARM-CPUs+GPU in a single device. The idea here is to use existing ARM architecture, but accelerate important functions. Developing a complex overlay would be quite a complicated project, so for many applications, it is only necessary to customize specific functions. But either way, best not delay, because who knows what AMD will do in the future, and like you mentioned, Intel(Altera) already abandoned everything except big data-center stuff..
- keikobadthebad 5y agoFor most problems an async 'coprocessor' that can use system memory over pcie is a good enough model. It's not tied to one platform and doesn't have to get involved with modifying the cpu architecture.
- therealcamino 5y agoThis has been tried on machines that had a writable control store, mostly in the 70's -- the Wikipedia page mentions a few of them. https://en.m.wikipedia.org/wiki/Control_store https://en.m.wikipedia.org/wiki/Control_store
- GrumpyYoungMan 5y agoSomething like that's already been thought of: Alessandro Forin's eMIPS project a few years back developed a prototype processor with a small FPGA fabric directly embedded into the processor that allows for creating custom instructions per application, e.g. https://www.researchgate.net/publication/255563459_A_Framework_for_Automated_Acceleration_of_Application_Binaries_on_eMIPS https://www.researchgate.net/publication/255563459_A_Framewo... among others. I don't think anything ever came of the idea; I imagine there's sharp limits on how much can fit into a CPU while still having decent performance. > "The ability to modify the data paths in a set of general purpose processor components (e.g. register banks, caches, integer ALU, float ALU, vector ALU, pipeline lookahead, etc) for specific applications by modifying the microcode would be a real leap forward." The latency and die cost of the connectivity for being able to rewire a "sea of execution units" is going to kill clock speed and performance.