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So my understanding of DDR5 has on chip ECC is needed due to the ever increasing need for -Ofast, will/does PCIe have the same requirements?
by nwmcsween 5y ago
So my understanding of DDR5 has on chip ECC is needed due to the ever increasing need for -Ofast, will/does PCIe have the same requirements?
- ksec 5y agoYes. Forward Error Correction (FEC) [1] . The Anandtech article wasn't in my feed when I submitted this. As it offers much more technical details. [1] https://www.anandtech.com/show/17203/pcie-60-specification-finalized-x16-slots-to-reach-128gbps https://www.anandtech.com/show/17203/pcie-60-specification-f...
- Dylan16807 5y agoYes it has that, but also no it's not the same. DDR5 has no link-level error correction. The faster and faster DDR5 bus is entirely unprotected on consumer devices.
- monocasa 5y agoThe on chip ECC for DDR5 isn't because of faster memory; it's because of denser memory. It can rowhammer itself, and fox it up silently. And the cheaper brands can start shipping chips with defects like they do with flash, relying on the ECC to paper over it.
- Taniwha 5y agoreading the articles I think that FEC is being used to protect link integrity - it's different from ECC on DRAM which is also protecting the contents (against things like row-hammer and cosmic rays)
- loeg 5y agoPCIe packets have always had error detection at the DLLP layer.