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Drop x86 as the instruction set. Make a fixed-width instruction set that is closer to their current micro-ops instruction set. Then provide a compatibility laye
by rocqua 5y ago
Drop x86 as the instruction set. Make a fixed-width instruction set that is closer to their current micro-ops instruction set. Then provide a compatibility layer to still run x86 based binaries.
- deleted 5y ago[deleted]
- Anarch157a 5y agoThey tried that with Itanium and we all know how it turned out.
- klelatti 5y agoThis is an interesting challenge - problem is even if they manage to move to a new ISA can they maintain their margins. I’d argue probably not: ie the problem is losing the ISA monopoly rather than a performance / technology disadvantage.
- MaxBarraclough 5y agoRight. Intel don't want a repeat of their Itanium. It's not a monopoly though, as there's also AMD.
- klelatti 5y agoYou’re right - I was being inexact re AMD. Itanium is an interesting historical example. I think Intel learnt the wrong lesson though: ‘cling to x86 at all costs’ when it was really that Itanium was just the wrong product. If they’d pushed a high quality Intel only 64 bit RISC design instead of Itanium at the time they might have succeeded. Edit: Just to expand on this a bit. At the time of Itanium they had a clear process lead. They could have offered the best server CPUs on an Intel only RISC ISA and invested heavily in helping customers migrate. Arm got customers from aarch32 to aarch64 seamlessly.
- Jyaif 5y agox86 is not the issue, their fabs are.
- _0w8t 5y agox86 makes decoders way more complex than fixed-width instruction set. In turn this leads to hacks like hyperthreading to allow to make decoders to run in parallel and utilize the whole core. Notice how it is absent from M1 since Apple was able to throw more decoders to single instruction flow and make single-threaded performance great.
- floatboth 5y agoHyperthreading isn't just about decoders, it's about occupying all the units as much as possible. Some Arm (RIP ThunderX2), POWER and SPARC server chips have 4-wide and even 8-wide SMT.
- freemint 5y agoAre you serious? If Intel does that they are just going to have to close a lot of fabs and die as a company.
- imtringued 5y agoMultiprocess python code massively benefits from hyperthreading and it's not bottlenecked by instruction decoding at all. It's bottlenecked by chasing pointers.