4 ms·
I think I agree it was a mistake/wart. I can understand the frustration of the GMP dev in the text - they get hit hard by this. The omission feels arbitary an
by kannanvijayan 5y ago
I think I agree it was a mistake/wart. I can understand the frustration of the GMP dev in the text - they get hit hard by this. The omission feels arbitary and capricious and a bit ideologically motivated. The defense of the choice seems like post-hoc rationalization.
RiscV looks like a nice ISA otherwise.
I wouldn't be surprised if it was eventually extended to add a set of variant instructions that wrote flags to an explicitly specified register.
- R0b0t1 5y agoShouldn't settle for less than interrupt on overflow tbh.
- Dylan16807 5y agoThat would probably be the easiest to add, wouldn't it?
- R0b0t1 5y agoIt should be, but they never do. It's really important for HPC workloads.