5 ms·

> This is in stark contrast with ARMv7's thumb, which was a literal separate CPU mode. This is disingenuous. arm32's Thumb-2 (which has been around since 2003)

• snvzz 5y ago
  Your statement does not run counter to mine quoted. Thumb-2 is better designed than Thumb was, but it is still a separate CPU mode. And it got far less use than it deserved, because of this. It doesn't do everything, and switching has a significant cost. This cost is in contrast with RISC-V's C extension.
  • lonjil 5y ago
    The ARMv8-M profile is Thumb-only, so on ARM microcontroller platforms there is no switching at all, and it does do everything, or at least everything you might want to do on a microcontroller, and has of course gotten a very large amount of use, considering how widely deployed those cores are.
    • Dylan16807 5y ago
      Is thumb-only particularly good for density, compared to being able to mix instruction sizes?
      • lonjil 5y ago
        Thumb has both 16-bit and 32-bit instructions.
        • Dylan16807 5y ago
          Oh, you meant thumb and thumb-2.
          • lonjil 5y ago
            "thumb-2" isn't really a thing. It's just an informal name from when more instructions were being added to thumb. it's still just thumb.
            • brucehoult 5y ago
              Thumb2 is a thing. Thumb is purely 16 bit instructions. Thumb2 is a mix of 16 bit and 32 bit instructions. As an illustrative example, in Thumb when the programmer writes "BL <offset>" or "BX <offset>" the assembler creates two undocumented 16 bit instructions next to each other which together have the desired effect. If you create those instructions yourself using e.g. .half directives (or if you're writing a JIT or compiler) then you can actually put other instructions between them, as long as you don't disturb the link register. In Thumb2 the bit patterns for BL and BX are the same, but they are an ACTUAL 32 bit instruction which can't be split up like it can in Thumb.
  • brandmeyer 5y ago
    Comparing RISC-V's "C" extension to classic Thumb when Thumb-2 is 17 years old is like comparing RISC-V's "V" extension to classic SSE when AVX-512 and SVE2 are already available. Its an insidious form of straw-man attack that preys on the reader's ignorance. > [Thumb-2] doesn't do everything, and switching has a significant cost. Technically true, but irrelevant. Cortex-M is thumb-only and can't switch. Cortex-A processors that support both Thumb and ARM instructions almost never actually switch at all.
    • AshamedCaptain 5y ago
      > Cortex-A processors that support both Thumb and ARM instructions almost never actually switch at all. That is not correct. At least before ARMv8, most processors that could run both Thumb and ARM switch very frequently, up the point some libraries could be Thumb while others were ARM (i.e. within the same task!). A lot (but not all) of Android for ARMv7 is actually Thumb(-2). This is why "interworking" is such a hot topic. Also, contrary to what the above poster says, switching does not have a "high cost", it is rather similar to the cost of a function call.
      • stephencanon 5y ago
        > it is rather similar to the cost of a function call. It literally is a function call, most of the time. And yeah, thumb-2 was the preferred encoding for 32b iOS and Android, and the only supported encoding for Windows phone, so it was used on billions of devices.
• Taniwha 5y ago
  The main distinction is that the 16-bit RISCV-C ISA exactly maps to existing 32-bit RISCV instructions, its implementation only occurs in the decode pipe stage
  • bpye 5y ago
    The C extension is that, an extension. A RISC-V core with the C extension should still support the long encoding as well. There is no 16-bit variant specified, only 32, 64 and 128. There is an E version of the ISA with a reduced register set, but this is a separate thing.
    • brucehoult 5y ago
      You are mixing up integer register size and instruction length. RISC-V has variants with 32 bit, 64 bit, or (not yet fully specified or implemented) 128 bit registers. RISC-V has instructions of length 32 bits and, optionally but almost universally, 16 bit length.
      • Taniwha 5y ago
        The E version only has half as many registers
      • bpye 5y ago
        Ah yes, I misunderstood the original comment as implying that RISC-V C had 16 bit register length, rather than opcode length.