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I'm not an expert on ISA and CPU internals, but an X86 instruction is not just "an instruction" anymore. Afaik, since the P6 arch Intel is using a fancy decoder

I'm not an expert on ISA and CPU internals, but an X86 instruction is not just "an instruction" anymore. Afaik, since the P6 arch Intel is using a fancy decoder to translate x86/-64 CISC into an internal RISC ISA (up to 4 u-ops per CISC instruction) and that internal ISA could be quite close to the RISC-V ISA for all I know. Instruction decoding and memory ordering can be a bit of nightmare on CISC ISAs and fewer macro-instructions are not automatically a win. I guess we'll eventually see in benchmarks. Even though Intel has had decades to refine their CPUs I'm quite excited to see where RISC-V is going.

theresistor 5y ago
As someone who is an expert on ISA and CPU internals, this meme of "X86 has an internal RISC" is an over-simplification that obscures reality. Yes, it decodes instructions into micro-ops. No, micro-ops are not "quite close to the RISC-V ISA". Macro fusion definitely has a place in microarchitecture performance, especially when you have to deal with a legacy ISA. RISC-V makes the very unusual choice of depending on it for performance, when most ISAs prefer to fix the problem upstream.
- jasonhansel 5y ago
  Indeed. Also not an expert, but relying on macro-op fusion in hardware is tricky IIRC since different implementors will (likely) choose different macro-ops, resulting in strange performance differences between otherwise-identical chips. Of course, you could start documenting "official" macro-ops that implementations should support, but at that point you're pretty much inventing a new ISA...
  - seoaeu 5y ago
    RISC-V does document "official" macro-ops that implementations are encouraged to support.
- evilos 5y ago
  > "X86 has an internal RISC" is an over-simplification that obscures reality Is it misleading though? I don't mind simplifications unless they are misleading. Would like to hear your criticisms of this meme.
  - imtringued 5y ago
    X86 processors could have an internal VLIW for all we know. The instruction length would be very small by Itanium standards but still. It could be anything.
    - evilos 5y ago
      Seems to me that the parent comment was claiming to know.
Tuna-Fish 5y ago
> but an X86 instruction is not just "an instruction" anymore. This is technically true but not really. Decoding into many instructions is mainly used for compatibility with the crufty parts of the x86 spec. In general, for anything other than rmw or locking a competent compiler or assembly writer will only very rarely emit instructions that compile to more than one uop. The way the frontend works, microcoded instructions are extraordinarily slow on real cpus. Modern x86 is basically a risc with a very complex decode, few extra useful complex operations tacked on, and piles and piles of old moldy cruft that no-one should ever touch.
- monocasa 5y ago
  X86 doesn't have to go to microcode to have multiple uOPs for an instruction. Most uarchs can spit out three or four uOPs per instruction before having to resort to the microcode ROM. Basically instructions that would only need one microcode ROM row in a purely microcoded design can be spit out of the fast decoders.
lonjil 5y ago
Most commonly used x86_64 instructions decode to only 1 or 2 µops, thus often also just as "complex" as the original instructions.

theresistor 5y ago

As someone who is an expert on ISA and CPU internals, this meme of "X86 has an internal RISC" is an over-simplification that obscures reality. Yes, it decodes instructions into micro-ops. No, micro-ops are not "quite close to the RISC-V ISA". Macro fusion definitely has a place in microarchitecture performance, especially when you have to deal with a legacy ISA. RISC-V makes the very unusual choice of depending on it for performance, when most ISAs prefer to fix the problem upstream.

jasonhansel 5y ago
Indeed. Also not an expert, but relying on macro-op fusion in hardware is tricky IIRC since different implementors will (likely) choose different macro-ops, resulting in strange performance differences between otherwise-identical chips. Of course, you could start documenting "official" macro-ops that implementations should support, but at that point you're pretty much inventing a new ISA...
- seoaeu 5y ago
  RISC-V does document "official" macro-ops that implementations are encouraged to support.
evilos 5y ago
> "X86 has an internal RISC" is an over-simplification that obscures reality Is it misleading though? I don't mind simplifications unless they are misleading. Would like to hear your criticisms of this meme.
- imtringued 5y ago
  X86 processors could have an internal VLIW for all we know. The instruction length would be very small by Itanium standards but still. It could be anything.
  - evilos 5y ago
    Seems to me that the parent comment was claiming to know.

Tuna-Fish 5y ago

> but an X86 instruction is not just "an instruction" anymore. This is technically true but not really. Decoding into many instructions is mainly used for compatibility with the crufty parts of the x86 spec. In general, for anything other than rmw or locking a competent compiler or assembly writer will only very rarely emit instructions that compile to more than one uop. The way the frontend works, microcoded instructions are extraordinarily slow on real cpus. Modern x86 is basically a risc with a very complex decode, few extra useful complex operations tacked on, and piles and piles of old moldy cruft that no-one should ever touch.

monocasa 5y ago
X86 doesn't have to go to microcode to have multiple uOPs for an instruction. Most uarchs can spit out three or four uOPs per instruction before having to resort to the microcode ROM. Basically instructions that would only need one microcode ROM row in a purely microcoded design can be spit out of the fast decoders.

lonjil 5y ago

Most commonly used x86_64 instructions decode to only 1 or 2 µops, thus often also just as "complex" as the original instructions.