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I use systemverilog daily, and it's very powerful. What does myhdl bring that's a game changer or even significant advantage in practice? SV has quite powerful
by tails4e 5y ago
I use systemverilog daily, and it's very powerful. What does myhdl bring that's a game changer or even significant advantage in practice? SV has quite powerful synatx, especially for verification, and it seems this replicates the basics of that but had to force it into an imperative box by using yield, etc to achieve concurrence, while SV has it by default - so SV is less complex in thst regard. Its an impressive achievement nonetheless, but I'm looking for a reason to switch.
- FPGAhacker 5y agoFor rtl there doesn’t seem to be much reason to use things like hardcaml and chisel. Testing is usually where the claimed advantage is. That and being open source. But as you say, SV is all about testing and verification. But the tools are closed source and expensive. I think the big win is the open source tooling that comes along with these efforts.
- IshKebab 5y agoSV has some quite crazy features and is absolutely massive. But I agree I think Python is a terrible replacement. By moving away from SV you lose a lot of tool support which is extremely important (can you do FPV in Python?) and Python is a pretty bad language anyway compared to its peers (Typescript, Kotlin, Rust, etc.)
- itsrainingagain 5y agoI use VHDL, not used Python. My understanding is that Python will be many times slower than VHDL, so verification tests that take the best part of a week would then take several weeks with Python. And being dynamically typed is fine if you are running a script that returns quickly, but what about it borking even hours into a simulation, when you can catch most dynamic type errors with stronger typed languages at compile time. Python doesn't look like a compelling replacement for VHDL, unless my understanding is off.