4 ms·

Luckily all DDR5 DIMMs will have on-chip ECC. My understanding is it's not a complete mitigation but does make exploitation harder.

snak 5y ago
Yes, the article mentions it: > What if I have ECC-capable DIMMs? > Previous work showed that due to the large number of bit flips in current DDR4 devices, ECC cannot provide complete protection against Rowhammer but makes exploitation harder.
- hinkley 5y ago
  It sounds to me like ECC isn't being included in the DDR5 spec due to magnanimity so much as because it doesn't function without it. That ECC has become 'load-bearing'. Does that mean we need an extended ECC to deal with critical systems that require additional robustness?
  - Legion 5y ago
    Who error checks the error checkers?
    - RedShift1 5y ago
      It's just a matter of time before someone finds a way to exploit the ECC part, calls it Hammerrow and brings us back to square one...
      - aaaaaaaaaaab 5y ago
        Rowhamming would be a better pun, as DDR5 uses a Hamming code for error correction.
eqvinox 5y ago
> My understanding is it's not a complete mitigation but does make exploitation harder. It won't. It's designed to counter silicon limitations to increased density, i.e. it's made to correct the errors that result from packing cells beyond the limit of error-free operation. The extra redundancy from on-chip ECC is intended to be "consumed" by the chip itself, and since this will allow optimizing chip manufacture to denser and cheaper, it's no question at all that it will get pushed to the very limit. There's still "classic" ECC for DDR5. 8 bits mapped to 9, terminated at the CPU which can look at things. That's what I want, need, and will buy. P.S.: Shame on Intel for still walling off desktop CPUs from ECC. https://ark.intel.com/content/www/us/en/ark/search/featurefilter.html?productType=873&0_StatusCodeText1=3,4&0_ECCMemory=True&2_MarketSegment=Desktop https://ark.intel.com/content/www/us/en/ark/search/featurefi...
- Dylan16807 5y ago
  > It won't. It's designed to counter silicon limitations to increased density, i.e. it's made to correct the errors that result from packing cells beyond the limit of error-free operation. I'd love to see actual parameters for the error correction codes, but DDR5 could pretty easily be a lot more robust than DDR4. When you have no error correction at all, you need ridiculously high reliability. Even if these new memory cells are have a much higher error rate, if they're designed to seamlessly handle a few bits in the same row flipping then the overall reliability could skyrocket. Edit: Oh, there's a paper from micron talking about DDR5 only having single bit correction internally. That's not as useful as it could be against attacks... > There's still "classic" ECC for DDR5. 8 bits mapped to 9 But Single Error Correction, Dual Error Detection is not enough to prevent attacks. Also because DDR5 uses a smaller width you actually need to map 8 bits to 10.
  - eqvinox 5y ago
    > I'd love to see actual parameters for the error correction codes Well, the spec is $369, but a PDF with some early discussion (rev 0.1…) says: DDR5 devices will implement internal Single Error Correction (SEC) ECC to improve the data integrity within the DRAM. The DRAM will use 128 data bits to compute the ECC code of 8 ECC Check Bits. However, I have no idea whether this is what got specified in the end. 8 ECC bits on 128 data bits would be half the amount of added redundancy compared to "classical" ECC. Note also it's not SECDED, just SEC, confirming the Micron paper you mentioned. > But Single Error Correction, Dual Error Detection is not enough to prevent attacks. The OP suggested monitoring for a sudden increase in ECC events, which hopefully this would work for. It's not a perfect countermeasure, just a statistical one, but I'll take what I can get... > Also because DDR5 uses a smaller width you actually need to map 8 bits to 10. Now that kinda makes it better, doesn't it? :)
kevin_thibedeau 5y ago
> Luckily all DDR5 DIMMs will have on-chip ECC Until someone starts building chips with fake ECC to boost profit.

snak 5y ago

Yes, the article mentions it: > What if I have ECC-capable DIMMs? > Previous work showed that due to the large number of bit flips in current DDR4 devices, ECC cannot provide complete protection against Rowhammer but makes exploitation harder.

hinkley 5y ago
It sounds to me like ECC isn't being included in the DDR5 spec due to magnanimity so much as because it doesn't function without it. That ECC has become 'load-bearing'. Does that mean we need an extended ECC to deal with critical systems that require additional robustness?
- Legion 5y ago
  Who error checks the error checkers?
  - RedShift1 5y ago
    It's just a matter of time before someone finds a way to exploit the ECC part, calls it Hammerrow and brings us back to square one...
    - aaaaaaaaaaab 5y ago
      Rowhamming would be a better pun, as DDR5 uses a Hamming code for error correction.

eqvinox 5y ago

> My understanding is it's not a complete mitigation but does make exploitation harder. It won't. It's designed to counter silicon limitations to increased density, i.e. it's made to correct the errors that result from packing cells beyond the limit of error-free operation. The extra redundancy from on-chip ECC is intended to be "consumed" by the chip itself, and since this will allow optimizing chip manufacture to denser and cheaper, it's no question at all that it will get pushed to the very limit. There's still "classic" ECC for DDR5. 8 bits mapped to 9, terminated at the CPU which can look at things. That's what I want, need, and will buy. P.S.: Shame on Intel for still walling off desktop CPUs from ECC. https://ark.intel.com/content/www/us/en/ark/search/featurefilter.html?productType=873&0_StatusCodeText1=3,4&0_ECCMemory=True&2_MarketSegment=Desktop https://ark.intel.com/content/www/us/en/ark/search/featurefi...

Dylan16807 5y ago
> It won't. It's designed to counter silicon limitations to increased density, i.e. it's made to correct the errors that result from packing cells beyond the limit of error-free operation. I'd love to see actual parameters for the error correction codes, but DDR5 could pretty easily be a lot more robust than DDR4. When you have no error correction at all, you need ridiculously high reliability. Even if these new memory cells are have a much higher error rate, if they're designed to seamlessly handle a few bits in the same row flipping then the overall reliability could skyrocket. Edit: Oh, there's a paper from micron talking about DDR5 only having single bit correction internally. That's not as useful as it could be against attacks... > There's still "classic" ECC for DDR5. 8 bits mapped to 9 But Single Error Correction, Dual Error Detection is not enough to prevent attacks. Also because DDR5 uses a smaller width you actually need to map 8 bits to 10.
- eqvinox 5y ago
  > I'd love to see actual parameters for the error correction codes Well, the spec is $369, but a PDF with some early discussion (rev 0.1…) says: DDR5 devices will implement internal Single Error Correction (SEC) ECC to improve the data integrity within the DRAM. The DRAM will use 128 data bits to compute the ECC code of 8 ECC Check Bits. However, I have no idea whether this is what got specified in the end. 8 ECC bits on 128 data bits would be half the amount of added redundancy compared to "classical" ECC. Note also it's not SECDED, just SEC, confirming the Micron paper you mentioned. > But Single Error Correction, Dual Error Detection is not enough to prevent attacks. The OP suggested monitoring for a sudden increase in ECC events, which hopefully this would work for. It's not a perfect countermeasure, just a statistical one, but I'll take what I can get... > Also because DDR5 uses a smaller width you actually need to map 8 bits to 10. Now that kinda makes it better, doesn't it? :)

kevin_thibedeau 5y ago

> Luckily all DDR5 DIMMs will have on-chip ECC Until someone starts building chips with fake ECC to boost profit.