5 ms·

Verilog Simulation with Verilator and SDL

76 points by WillFlux 5y ago

rtpg 5y ago
This looks really helpful! I have been working on FPGA stuff and have never really been able to figure out how to tie the knot with Verilator, even though I knew this was theoretically possible.
- WillFlux 5y ago
  I can empathise. I was aware of Verilator for ages before I started simulating my own designs with it. The Verilator documentation is good, but it can do so much that it's hard to know where to start.
Arch-TK 5y ago
I wish there was more stuff for VHDL. It always seems to be left out despite being fundamentally a superior option over Verilog.
- mtoner23 5y ago
  Fundementally? Bold claim
  - henrikeh 5y ago
    Verilog is weakly typed and VHDL is strong. That is already a pretty big deal when dealing with vector signals, where Verilog happily assigns a 32-bit signal to a 16-bit signal. VHDL also supports defining record types, such that a collection of signals can be assigned together.
    - brandmeyer 5y ago
      SystemVerilog also supports composite types using interfaces. Using Verilator as a linter will aggressively warn you about signal width mismatches. Most complaints about Verilog from VHDL people come from outdated notions of the current state of the language and its tooling.
      - WillFlux 5y ago
        I also have a post on Verilog Lint with Verilator: https://projectf.io/posts/verilog-lint-with-verilator/ https://projectf.io/posts/verilog-lint-with-verilator/
      - anfilt 5y ago
        VHDLs type system is pretty rock solid it’s based off Ada after all. Which if you have looked at in any detail its a great type system! I dont like the begin end style syntax and some the verbosity that entails with VHDL. However, I would rather create designs in VHDL than verilog when given the choice.
    - beefok 5y ago
      I come from a VHDL background (the industry I work in is purely VHDL), but recently I've been enjoying Systemverilog in my personal projects and it fixes a lot of these issues! You can even do: typedef enum bit[1:0] { my_one, my_two, my_three, my_four } my_enum; typedef struct packed { my_enum b, bit [3:0] x } my_struct my_struct.b <= my_three; etc... It's been a nice path since I last dealt with Verilog. The concept of interfaces makes struct/vector input/output even nicer.
      - UncleOxidant 5y ago
        It's true that SystemVerilog fixed a lot of Verilog's deficiencies and took it more in the direction of VHDL. But a lot of free tools don't support SystemVerilog.
        beefok 5y ago
        Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "verilog" synthesis tools actually synthesize SystemVerilog. Out of curiosity what tool are you referring to? Thanks!
        mhh__ 5y ago
        There isn't much support if any in open source tools, if free means free software.
        beefok 5y ago
        I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog. What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.
        gchadwick 5y ago
        There's few open source tools for any HDL full stop. Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/ https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).
  - imglorp 5y ago
    One nice feature of VHDL we could use in modern software is different styles of descriptions of the same object in the same model: behavioral, structural, dataflow. The model can be given to tools operating at different levels: synthesis, simulation, verification etc.
  - IshKebab 5y ago
    I don't know much about VHDL but Verilog (and SystemVerilog) are definitely fundamentally insane languages. Any time VHDL comes up it's usually in the context of "this isn't a problem in VHDL". (But also "this would be way more verbose in VHDL")
- jleahy 5y ago
  Both are awful languages, but Verilog is an awful language with broad industry support.
  - anfilt 5y ago
    VHDL and Verilog both have industry support. VHDL is much better if I had to pick one though. It seems to be though a lot the open source stuff seems to pick Verilog for some reason. Most commercial tools support both HDLs.
    - artisanspam 5y ago
      While Verilog is not SystemVerilog, it’s more or less a subset of it. And SystemVerilog had much more industry support for design verification. So if I were to design some open source software for HDLs, that reason alone would make VHDL a non-starter.
      - NextHendrix 5y ago
        SystemVerilog and UVM are perfectly capable of being used to verify VHDL designs. I should also add that if you wanted to use a single language for everything OSVVM is excellent.
        artisanspam 5y ago
        Sure it's capable, but there's certainly a cost of having to use multiple languages in your test bench/DUT. I'd argue that's one of the reasons why Verilator, CocoTB, Chisel, etc. haven't taken off in the "traditional" semiconductor industry (i.e. not FPGAs).
      - teleforce 5y ago
        Verilog is now officially the subset of SystemVerilog since 2009 [1]. The same can be said now for C since it's supported in both C++ and D compiler. [1] https://standards.ieee.org/project/1800.html https://standards.ieee.org/project/1800.html
    - 5y ago
- aortega 5y ago
  VHDL has horrible syntax. Verilog has a much more friendly c-like syntax, even if the friendliness is only a trap.
  - Arch-TK 5y ago
    I imagine you think pascal and ada have horrible syntax too? For me, the syntax is ideal. On the plus side VHDL seems to have actually been designed with the intention of being used for FPGA designs. Verilog on the other hand just seems like a hack in comparison.
    - leche 5y ago
      The opposite is true. VHDL was originally designed as an implementation-agnostic documentation and description language.
  - UncleOxidant 5y ago
    And that's why Verilog has mostly "won". But syntax isn't the whole story of a language. VHDL's type system is much superior to Verilog's. I once worked for an EDA company and we had a product that emitted HDL (Verilog or VHDL depending on what the user chose). At some point we had requests from customers to fix linting warnings in the generated code. My job was to placate the linter. For the VHDL code generator there wasn't much to fix - just not a lot of linting problems due to the type system. For the verilog code generator, though, there were lots of linting warnings to fix.
- anfilt 5y ago
  I was gonna say something similar. VHDL’s type system for starters is way better (thanks to it being based off Ada) While not a big fan of the begin end style syntax, it definitely is better than verilog in my experience. I find interesting so many open source projects like this target Verilog. It also kinda bugs me.
  - dnautics 5y ago
    at the same time, if you're transpiling from something else, verilog is MUCH better than VHDL because as a language it has a much smaller surface area. Modulo "HDL is different because everything is synchronous" and the testing DSL, You can learn most of verilog in a day, not so much VHDL.
fouric 5y ago
I did something kind of like this for a college project. We were taking a course on FPGA soft-processors, and for our final project, we had to build A Thing. My team chose to reimplement Space Invaders. The soft-core was supported by a C compiler, so we wrote the game in C, with carefully-chosen functions for graphics rendering containing #ifdefs that gated either direct memory accesses (for the FPGA VGA hardware) or SDL calls. Our "init()" function would initialize the VGA hardware on the FPGA, and create an SDL window when compiled on a computer with an OS. Using this, the hardware and software people were able to work together in parallel, and we won best project for our class, with a grand prize of "we'll show your cool project to the next classes". As I recall, we wrote most of the game using SDL backend, and only tested it on "real" hardware a few days before the final project. We found a single bug (during the integration) that took us on the order of half an hour to debug, and that was that.
liaukovv 5y ago
Is it an alternative to modelsim? Or something different?
- gchadwick 5y ago
  Sort of. Verilator can simulator a subset of SystemVerilog, mostly that which is synthesizable (though work is on-going to expand its capabilities so it can run UVM code). So it's a replacement for modelsim if you're just using it to run your actual design RTL. You need to build a synthesisable testbench or write one in C++ (or check cocotb: https://github.com/cocotb/cocotb https://github.com/cocotb/cocotb)

76 points by WillFlux 5y ago

rtpg 5y ago

This looks really helpful! I have been working on FPGA stuff and have never really been able to figure out how to tie the knot with Verilator, even though I knew this was theoretically possible.

WillFlux 5y ago
I can empathise. I was aware of Verilator for ages before I started simulating my own designs with it. The Verilator documentation is good, but it can do so much that it's hard to know where to start.

Arch-TK 5y ago

I wish there was more stuff for VHDL. It always seems to be left out despite being fundamentally a superior option over Verilog.

mtoner23 5y ago
Fundementally? Bold claim
- henrikeh 5y ago
  Verilog is weakly typed and VHDL is strong. That is already a pretty big deal when dealing with vector signals, where Verilog happily assigns a 32-bit signal to a 16-bit signal. VHDL also supports defining record types, such that a collection of signals can be assigned together.
  - brandmeyer 5y ago
    SystemVerilog also supports composite types using interfaces. Using Verilator as a linter will aggressively warn you about signal width mismatches. Most complaints about Verilog from VHDL people come from outdated notions of the current state of the language and its tooling.
    - WillFlux 5y ago
      I also have a post on Verilog Lint with Verilator: https://projectf.io/posts/verilog-lint-with-verilator/ https://projectf.io/posts/verilog-lint-with-verilator/
    - anfilt 5y ago
      VHDLs type system is pretty rock solid it’s based off Ada after all. Which if you have looked at in any detail its a great type system! I dont like the begin end style syntax and some the verbosity that entails with VHDL. However, I would rather create designs in VHDL than verilog when given the choice.
  - beefok 5y ago
    I come from a VHDL background (the industry I work in is purely VHDL), but recently I've been enjoying Systemverilog in my personal projects and it fixes a lot of these issues! You can even do: typedef enum bit[1:0] { my_one, my_two, my_three, my_four } my_enum; typedef struct packed { my_enum b, bit [3:0] x } my_struct my_struct.b <= my_three; etc... It's been a nice path since I last dealt with Verilog. The concept of interfaces makes struct/vector input/output even nicer.
    - UncleOxidant 5y ago
      It's true that SystemVerilog fixed a lot of Verilog's deficiencies and took it more in the direction of VHDL. But a lot of free tools don't support SystemVerilog.
      - beefok 5y ago
        Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "verilog" synthesis tools actually synthesize SystemVerilog. Out of curiosity what tool are you referring to? Thanks!
        mhh__ 5y ago
        There isn't much support if any in open source tools, if free means free software.
        beefok 5y ago
        I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog. What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.
        gchadwick 5y ago
        There's few open source tools for any HDL full stop. Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/ https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).
- imglorp 5y ago
  One nice feature of VHDL we could use in modern software is different styles of descriptions of the same object in the same model: behavioral, structural, dataflow. The model can be given to tools operating at different levels: synthesis, simulation, verification etc.
- IshKebab 5y ago
  I don't know much about VHDL but Verilog (and SystemVerilog) are definitely fundamentally insane languages. Any time VHDL comes up it's usually in the context of "this isn't a problem in VHDL". (But also "this would be way more verbose in VHDL")
jleahy 5y ago
Both are awful languages, but Verilog is an awful language with broad industry support.
- anfilt 5y ago
  VHDL and Verilog both have industry support. VHDL is much better if I had to pick one though. It seems to be though a lot the open source stuff seems to pick Verilog for some reason. Most commercial tools support both HDLs.
  - artisanspam 5y ago
    While Verilog is not SystemVerilog, it’s more or less a subset of it. And SystemVerilog had much more industry support for design verification. So if I were to design some open source software for HDLs, that reason alone would make VHDL a non-starter.
    - NextHendrix 5y ago
      SystemVerilog and UVM are perfectly capable of being used to verify VHDL designs. I should also add that if you wanted to use a single language for everything OSVVM is excellent.
      - artisanspam 5y ago
        Sure it's capable, but there's certainly a cost of having to use multiple languages in your test bench/DUT. I'd argue that's one of the reasons why Verilator, CocoTB, Chisel, etc. haven't taken off in the "traditional" semiconductor industry (i.e. not FPGAs).
    - teleforce 5y ago
      Verilog is now officially the subset of SystemVerilog since 2009 [1]. The same can be said now for C since it's supported in both C++ and D compiler. [1] https://standards.ieee.org/project/1800.html https://standards.ieee.org/project/1800.html
  - 5y ago
aortega 5y ago
VHDL has horrible syntax. Verilog has a much more friendly c-like syntax, even if the friendliness is only a trap.
- Arch-TK 5y ago
  I imagine you think pascal and ada have horrible syntax too? For me, the syntax is ideal. On the plus side VHDL seems to have actually been designed with the intention of being used for FPGA designs. Verilog on the other hand just seems like a hack in comparison.
  - leche 5y ago
    The opposite is true. VHDL was originally designed as an implementation-agnostic documentation and description language.
- UncleOxidant 5y ago
  And that's why Verilog has mostly "won". But syntax isn't the whole story of a language. VHDL's type system is much superior to Verilog's. I once worked for an EDA company and we had a product that emitted HDL (Verilog or VHDL depending on what the user chose). At some point we had requests from customers to fix linting warnings in the generated code. My job was to placate the linter. For the VHDL code generator there wasn't much to fix - just not a lot of linting problems due to the type system. For the verilog code generator, though, there were lots of linting warnings to fix.
anfilt 5y ago
I was gonna say something similar. VHDL’s type system for starters is way better (thanks to it being based off Ada) While not a big fan of the begin end style syntax, it definitely is better than verilog in my experience. I find interesting so many open source projects like this target Verilog. It also kinda bugs me.
- dnautics 5y ago
  at the same time, if you're transpiling from something else, verilog is MUCH better than VHDL because as a language it has a much smaller surface area. Modulo "HDL is different because everything is synchronous" and the testing DSL, You can learn most of verilog in a day, not so much VHDL.

fouric 5y ago

I did something kind of like this for a college project. We were taking a course on FPGA soft-processors, and for our final project, we had to build A Thing. My team chose to reimplement Space Invaders. The soft-core was supported by a C compiler, so we wrote the game in C, with carefully-chosen functions for graphics rendering containing #ifdefs that gated either direct memory accesses (for the FPGA VGA hardware) or SDL calls. Our "init()" function would initialize the VGA hardware on the FPGA, and create an SDL window when compiled on a computer with an OS. Using this, the hardware and software people were able to work together in parallel, and we won best project for our class, with a grand prize of "we'll show your cool project to the next classes". As I recall, we wrote most of the game using SDL backend, and only tested it on "real" hardware a few days before the final project. We found a single bug (during the integration) that took us on the order of half an hour to debug, and that was that.

liaukovv 5y ago

Is it an alternative to modelsim? Or something different?

gchadwick 5y ago
Sort of. Verilator can simulator a subset of SystemVerilog, mostly that which is synthesizable (though work is on-going to expand its capabilities so it can run UVM code). So it's a replacement for modelsim if you're just using it to run your actual design RTL. You need to build a synthesisable testbench or write one in C++ (or check cocotb: https://github.com/cocotb/cocotb https://github.com/cocotb/cocotb)