4 ms·
@tialaramex is making their point rather poorly, using the term "expensive" without explaining how, and being a bit aggressive about it. The more ASes that exi
by unethical_ban 5y ago
@tialaramex is making their point rather poorly, using the term "expensive" without explaining how, and being a bit aggressive about it.
The more ASes that exist, the more routes need to be propagated. If every household were theoretically assigned a network that they could take with them anywhere, and advertise, a well-connected router would have millions and millions of routes to track and forward.
One of the goals of IPv6 was to make the Internet more hierarchical to avoid this.
I agree with your point. I should be able to get a static PD from my ISP (a /56 or /60 easily) and that should stay the same for all time, given a MAC address. In other words, PD should be stateful.
I have thought about setting up my LAN with "Unique Local Addresses" and doing NAT66 if I can ever manage to get a public IPV6 address from my ISP.
- vetinari 5y agoYou don't need to do NAT66; just enable ULA. Interfaces can have multiple IPv6 addresses, not just one. So you will get your static local addresses and for outbound traffic, a random globally routed address from the currently assigned prefix would be used.
- Dylan16807 5y agoI know routing table bloat is annoying and it's hard to do tons of routes in an ultra-fast way, but I do want to point out that "millions and millions of routes" translates to "tens and tens of megabytes".
- Dagger2 5y agoBut if you're doing fast hardware routing, that's tens and tens of megabytes of TCAM, not DRAM. It's more akin to CPU cache in terms of latency, capacity and cost.
- Dylan16807 5y agoYou can get a $600 Epyc with 128MB of cache. That shouldn't be too much compared to the tier of router we're talking about, right?
- Dagger2 5y agoThat's L3 cache though; they only have 0.5 MB of L2 cache per core. I'm not really sure how much each of these types of memory cost, but I did find [1] which says "The cost of TCAM is also about 30 times more per bit of storage than SRAM". That suggests a CPU with something more like 0.5-1 GB of L3 cache would be a closer comparison. [1] https://research.ijcaonline.org/volume115/number7/pxc3902299.pdf https://research.ijcaonline.org/volume115/number7/pxc3902299...