7 ms·

Section 5.3 of the Nios V Quickstart Guide (https://www.intel.com/content/www/us/en/programmable/documentation/jmv1629188568604.html#fyy1630546382179 https://ww

Section 5.3 of the Nios V Quickstart Guide (https://www.intel.com/content/www/us/en/programmable/documentation/jmv1629188568604.html#fyy1630546382179 https://www.intel.com/content/www/us/en/programmable/documen...) has a waveform of the instruction AXI bus. I think the memory system in that example has a 3 cycle memory access latency, and the CPU waits for one instruction to arrive before requesting the next one. I'm almost surprised that they manage 0.464! The Coremark score doesn't make any sense indeed. Where did you find these numbers?

Dylan16807 5y ago
> I think the memory system in that example has a 3 cycle memory access latency, and the CPU waits for one instruction to arrive before requesting the next one. I'm almost surprised that they manage 0.464! I'm sure the 4+2KB of cache helps. > Where did you find these numbers? https://www.intel.com/content/www/us/en/programmable/documentation/lae1629183268014.html https://www.intel.com/content/www/us/en/programmable/documen... https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf https://www.intel.com/content/dam/www/programmable/us/en/pdf...