What the semantics to the programmer (AI compiler) look like? Arbitrary bitwidth loads from Arbitrary bit offsets? Basically https://www.cplusplus.com/referenc

What the semantics to the programmer (AI compiler) look like? Arbitrary bitwidth loads from Arbitrary bit offsets? Basically https://www.cplusplus.com/reference/cstring/strncpy/ https://www.cplusplus.com/reference/cstring/strncpy/ I'd like to see structs be representable in the CPU and the CPU would generate all the load store instructions, stencil computations would have a hardware level description. Could you see supporting this on say a RISC-V cpu? Or would it be a new ISA designed to support bit addressability? If you patched it in, what would it look like? What if memory was multidimensional? It would be excellent for storing extra metadata, counters, permission bits, provenance, event listeners.