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Neat paper. I designed the ALU for a fabbed university microprocessor as a student. Something I have always thought would be interesting is if memory was more

Neat paper. I designed the ALU for a fabbed university microprocessor as a student. Something I have always thought would be interesting is if memory was more bit addressable. Would we find non-obvious efficiencies, like the ones in the Shifter paper, by generalizing from byte to bit addressing? * More aesthetically pleasing (to me!) * Flexible bit-scalable integer ranges * Flexible bit-scalable floating point precisions * More efficient use of data layout and transfer * Other non-obvious benefits? Giving up 3 bits of 64-bit addresses for bit level precision doesn't seem like a big disadvantage for address space. 2^64 bytes = 18,466,744,073,709,551,616 bytes = 18 quintillion bytes = 18 EiB vs: 2^64 bits = 18,466,744,073,709,551,616 bits = 2,305,843,009,213,693,952 bytes = 2.3 quintillion bytes = 2.3 EiB

sitkack 5y ago
What the semantics to the programmer (AI compiler) look like? Arbitrary bitwidth loads from Arbitrary bit offsets? Basically https://www.cplusplus.com/reference/cstring/strncpy/ https://www.cplusplus.com/reference/cstring/strncpy/ I'd like to see structs be representable in the CPU and the CPU would generate all the load store instructions, stencil computations would have a hardware level description. Could you see supporting this on say a RISC-V cpu? Or would it be a new ISA designed to support bit addressability? If you patched it in, what would it look like? What if memory was multidimensional? It would be excellent for storing extra metadata, counters, permission bits, provenance, event listeners.
aDfbrtVt 5y ago
A couple of obvious reasons you can't reduce the address resolution to single bit: - Mux complexity would be drastically increased which costs area, power and latency. - Additional gearboxing around SRAM's would be far more complex.
- Nevermark 5y ago
  We already have shift-N instructions, although nothing is being shifted in, just bits shifted out. You might be right, but a long rethink of all that would be worth it before concluding that. I would say I am holding onto hope, but I doubt this will happen any time soon. :)

sitkack 5y ago

What the semantics to the programmer (AI compiler) look like? Arbitrary bitwidth loads from Arbitrary bit offsets? Basically https://www.cplusplus.com/reference/cstring/strncpy/ https://www.cplusplus.com/reference/cstring/strncpy/ I'd like to see structs be representable in the CPU and the CPU would generate all the load store instructions, stencil computations would have a hardware level description. Could you see supporting this on say a RISC-V cpu? Or would it be a new ISA designed to support bit addressability? If you patched it in, what would it look like? What if memory was multidimensional? It would be excellent for storing extra metadata, counters, permission bits, provenance, event listeners.

aDfbrtVt 5y ago

A couple of obvious reasons you can't reduce the address resolution to single bit: - Mux complexity would be drastically increased which costs area, power and latency. - Additional gearboxing around SRAM's would be far more complex.

Nevermark 5y ago
We already have shift-N instructions, although nothing is being shifted in, just bits shifted out. You might be right, but a long rethink of all that would be worth it before concluding that. I would say I am holding onto hope, but I doubt this will happen any time soon. :)