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I was really surprised by this cache design, in a good way. It's a very interesting innovation, one of those that is simple once you hear it but nobody (as far
by buildbot 5y ago
I was really surprised by this cache design, in a good way. It's a very interesting innovation, one of those that is simple once you hear it but nobody (as far as I know?) has tried this approach yet. I think it's very clever for a large distributed system like the Z mainframes;
It would be fun to build some Network on Chip FPGA designs using this approach to model how it would perform!
- api 5y agoOne thing I wish modern multi core chips had was some way to just directly transfer core to core. That would be really interesting, though I suppose it might be really hard to make it play nice with OS abstractions. Might only be useful in specialized HPC applications.
- tux3 5y agoWell.. you can play cacheline ping pong between cores today! No going to DRAM, straight from core to core. But I'm curious what sort of algorithm you have in mind that needs to spend a lot of time moving data between cores. Maybe some sort of algorithm that needs to alternate short steps of aggregating intermediate data and re-distributing the result to every core, in a loop? So, the shape of the problem that would fit this solution is not obvious to me :) Embarassingly parallel algorithms are the ideal. The less communication, the less Amdhal's tax costs you.
- Jweb_Guru 5y agoSome general purposes CPUs do have stuff like that, but apparently it's rarely used and often buggy due to neither being well tested nor going through the usual cache protocol.
- shaklee3 5y agoGPUs have this with warp instructions
- jyounker 5y agoEverything old is new again. In the 90's Kendall Square Research built modular supercomputers based around using nothing but cache. https://en.wikipedia.org/wiki/Kendall_Square_Research https://en.wikipedia.org/wiki/Kendall_Square_Research
- buildbot 5y agoThis is really awesome, thanks for the link!