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Dumb question: since memory bandwidth is clearly a bottleneck in many server workloads, why don't chip manufacturers make CPUs with 20 memory channels instead o

Dumb question: since memory bandwidth is clearly a bottleneck in many server workloads, why don't chip manufacturers make CPUs with 20 memory channels instead of just 6-10, as in current CPUs?

PragmaticPulp 5y ago
> Dumb question: since memory bandwidth is clearly a bottleneck in many server workloads, why don't chip manufacturers make CPUs with 20 memory channels instead of just 6-10, as in current CPUs? It gets difficult to fit it all and make it work. An 8-channel DDR4 memory controller already has 512 pins just for data bits, and that's before you deal with all of the necessary grounding pins and all of the other signal lines required to interface with memory chips. There are rumors that AMD's next generation server CPUs will support 12-channel DDR5. The expanded memory channels and other features require a socket with 6096 pins. That's a lot of interfaces to squeeze through a socket. A hypothetical 20-channel CPU would also require you to install RAM in multiples of 20 sticks to populate every channel. You can theoretically get 16 channels of memory bandwidth in a single, dual-socket system if each socket has an 8-channel memory controller. Dual-socket AMD systems have a theoretical upper limit memory bandwidth around 300GB (big B) per second. In reality, not as many applications are constrained my memory bandwidth as you might expect. CPU vendors are adding additional cache to work around the memory issue somewhat. As long as the application isn't constantly streaming bytes into and out of memory (as in the CDN example), it will eventually have to stop to work on the data, allowing the CPU a chance to cache some additional data from main memory and hide the memory bandwidth bottleneck somewhat.
wmf 5y ago
Here you go; just don't ask what it costs. https://www.linleygroup.com/newsletters/newsletter_detail.php?num=6070&year=2019&tag=3 https://www.linleygroup.com/newsletters/newsletter_detail.ph... https://fuse.wikichip.org/news/2893/ibm-adds-power9-aio-pushes-for-an-open-memory-agnostic-interface/ https://fuse.wikichip.org/news/2893/ibm-adds-power9-aio-push...
Dylan16807 5y ago
Most of the people that really need a certain amount of bandwidth per core are probably better off buying CPUs with fewer cores.
nwmcsween 5y ago
It's because dram currently is a parrellel interface, think ata ribbons vs serial ATA (sata). The future ram interface will be serial.
- wmf 5y ago
  Intel went "backwards" from FBD to DDR so it's not obvious that serial is the future.

Dumb question: since memory bandwidth is clearly a bottleneck in many server workloads, why don't chip manufacturers make CPUs with 20 memory channels instead of just 6-10, as in current CPUs?

PragmaticPulp 5y ago

> Dumb question: since memory bandwidth is clearly a bottleneck in many server workloads, why don't chip manufacturers make CPUs with 20 memory channels instead of just 6-10, as in current CPUs? It gets difficult to fit it all and make it work. An 8-channel DDR4 memory controller already has 512 pins just for data bits, and that's before you deal with all of the necessary grounding pins and all of the other signal lines required to interface with memory chips. There are rumors that AMD's next generation server CPUs will support 12-channel DDR5. The expanded memory channels and other features require a socket with 6096 pins. That's a lot of interfaces to squeeze through a socket. A hypothetical 20-channel CPU would also require you to install RAM in multiples of 20 sticks to populate every channel. You can theoretically get 16 channels of memory bandwidth in a single, dual-socket system if each socket has an 8-channel memory controller. Dual-socket AMD systems have a theoretical upper limit memory bandwidth around 300GB (big B) per second. In reality, not as many applications are constrained my memory bandwidth as you might expect. CPU vendors are adding additional cache to work around the memory issue somewhat. As long as the application isn't constantly streaming bytes into and out of memory (as in the CDN example), it will eventually have to stop to work on the data, allowing the CPU a chance to cache some additional data from main memory and hide the memory bandwidth bottleneck somewhat.

wmf 5y ago

Here you go; just don't ask what it costs. https://www.linleygroup.com/newsletters/newsletter_detail.php?num=6070&year=2019&tag=3 https://www.linleygroup.com/newsletters/newsletter_detail.ph... https://fuse.wikichip.org/news/2893/ibm-adds-power9-aio-pushes-for-an-open-memory-agnostic-interface/ https://fuse.wikichip.org/news/2893/ibm-adds-power9-aio-push...

Dylan16807 5y ago

Most of the people that really need a certain amount of bandwidth per core are probably better off buying CPUs with fewer cores.

nwmcsween 5y ago

It's because dram currently is a parrellel interface, think ata ribbons vs serial ATA (sata). The future ram interface will be serial.

wmf 5y ago
Intel went "backwards" from FBD to DDR so it's not obvious that serial is the future.