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I think (?) the first generation of TPU and Coral chips were designed using Chisel. There was a good presentation done by Google a while back but I will have to

• ekiwi 5y ago
  It was in fact the EdgeTPU (which is different from the TPU used in data centers). The talk from a google engineer can be found on youtube: https://www.youtube.com/watch?v=x85342Cny8c https://www.youtube.com/watch?v=x85342Cny8c Please note that they were using a version of Chisel from 5+ years ago and many things have changed since then. It is still true though that Chisel can be hard to learn for typical hardware engineers, which is why it may be best suited for small and highly dedicated teams rather then large hardware companies. [EDIT] Here is a talk from a solo-developer using the latest version of Chisel: https://www.youtube.com/watch?v=Wst8IoYRWKo https://www.youtube.com/watch?v=Wst8IoYRWKo
  • Rochus 5y ago
    Some interesting quotes from the presentation: "frankly, most hardware engineers don't really get passed this yellow [Chisel learning] curve" "Chisel makes the long pole of chip design longer" "the productivity gains we might have had on the design side were more than lost on the verification side" "It might be a hard sell for other projects to adopt Chisel [...] there were a buch of dark periods, mostly".
    • cushychicken 5y ago
      the productivity gains we might have had on the design side were more than lost on the verification side This makes sense. Without a complementary lift to verification capability, a lot of the design side wins don't gain you much.
      • aDfbrtVt 5y ago
        I'm very surprised by the reported cost to verification. One of the major reasons to move to a high level synthesis design strategy is to ensure equivalence between your models and RTL. I have experience with C++ HLS and it has enabled massive reductions in verification time.
        • ekiwi 5y ago
          Chisel is not HLS. It is a Scala library that lets you generate circuits on an RTL abstraction level. That means that you explicitly define every state element like registers and memories. But you can generate N registers inside a loop (or a map/foreach) instead of only 1 at a time. In HLS the compiler needs to somehow infer your registers and memories. That said, I think one of the problems the google team was struggling with is that in traditional HW development there is design and a separate verification team. The design team bought into Chisel since it would let them generate hardware more quickly, but the verification team just tried to apply their traditional verification methods on the _generated_ Verilog. This is almost like trying to test the assembly that a C++ compiler generates instead of trying to test the C++ program since all your testing infrastructure is setup for testing assembly code and that is "what we have always been doing". In order to catch verification up to modern Hardware Construction Languages [0] we need more powerful verification libraries that can allow us to build tests that can automatically adapt to the parameters that were supplied to the hardware generator. There are different groups working on this right now. The jury is still out on how to best solver the "verification gap". In case you are interested: - https://github.com/chiselverify/chiselverify https://github.com/chiselverify/chiselverify - https://github.com/leonardt/fault https://github.com/leonardt/fault - https://github.com/ucb-bar/chisel-testers2/ https://github.com/ucb-bar/chisel-testers2/ I am probably missing some approaches from the nmigen world that I am not familiar with. You can always write cocotb [1] tests in python, but I am not sure if they can directly interface with nmigen generators to adapt to their parameterization. [0] besides Chisel, there is also https://github.com/nmigen/nmigen https://github.com/nmigen/nmigen and https://github.com/SpinalHDL/SpinalHDL https://github.com/SpinalHDL/SpinalHDL [1] https://github.com/cocotb/cocotb https://github.com/cocotb/cocotb
          • Rochus 5y ago