2 ms·
For those that didn't read/skim to the end: > Alright, if you’ve got this far I’m sure you’ve realised that the whole project is something of a joke.
by mattowen_uk 5y ago
For those that didn't read/skim to the end:
> Alright, if you’ve got this far I’m sure you’ve realised that the whole project is something of a joke.
- joezydeco 5y agoWhat really would have sealed the deal was implementing this in WASM, translating it into Verilog, then burning it into an FPGA