4 ms·

It is not actually incompatible within the same die, IBM z15 uses eDRAM for the L1 caches even.

• baybal2 5y ago
  Not L1, but L2 and on. A very curious case, and a very clever hackery with a custom SOI process. It's still very, very far from coming to mainstream chips.
  • jahnu 5y ago
    It says L1 here "Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM." https://en.m.wikipedia.org/wiki/IBM_z15_(microprocessor) https://en.m.wikipedia.org/wiki/IBM_z15_(microprocessor)
    • baybal2 5y ago
      I got L1 being SRAM from here https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-adds-hundreds-of-megabytes-of-cache/ https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr...
      • jahnu 5y ago
        IBM's technical guide also says it's eDRAM https://www.redbooks.ibm.com/redbooks/pdfs/sg248851.pdf https://www.redbooks.ibm.com/redbooks/pdfs/sg248851.pdf
        • rbanffy 5y ago
          It's almost sad to see the x86s compared to the IBM mainframes...
  • amelius 5y ago
    What is the main hurdle? Why are these processes incompatible?