3 ms·
Main memory, if you mean DRAM, no. DRAM is incompatible with the logic family used in CPU making, though attempts were numerous at trying to work around that.
by baybal2 5y ago
Main memory, if you mean DRAM, no.
DRAM is incompatible with the logic family used in CPU making, though attempts were numerous at trying to work around that. Every few years, there are somebody coming with claims of passable CMOS+DRAM tech, but none got adoption so far.
- my123 5y agoIt is not actually incompatible within the same die, IBM z15 uses eDRAM for the L1 caches even.
- baybal2 5y agoNot L1, but L2 and on. A very curious case, and a very clever hackery with a custom SOI process. It's still very, very far from coming to mainstream chips.
- jahnu 5y agoIt says L1 here "Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM." https://en.m.wikipedia.org/wiki/IBM_z15_(microprocessor) https://en.m.wikipedia.org/wiki/IBM_z15_(microprocessor)
- baybal2 5y agoI got L1 being SRAM from here https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density-adds-hundreds-of-megabytes-of-cache/ https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr...
- amelius 5y agoWhat is the main hurdle? Why are these processes incompatible?
- geertj 5y agoGenuinely curious, could you say why logic and dram on the same chip are incompatible?
- adwn 5y agoThat's because high-density logic and high-density DRAM require very different steps during wafer fabrication.
- baybal2 5y agoFor practical considerations, both DRAM, and CMOS need a lot of steps, and both of them are already dialled closed to thermal limits of materials. So if you just first make CMOS, and leave empty space nearby protected by something to do DRAM later, it will be very hard to fit into the tiny remaining thermal budget past which CMOS devices will turn into schmoo.
- colejohnson66 5y agoBasically, at the low nanometer range,[a] if you want on-chip DRAM, it’d be a separate die (“chiplet”) connected by the substrate [a]: what’s the upper limit? As in, when does it not work anymore? For example, would it work at 100+ nm?
- baybal2 5y agoI am not a specialist, but I think I can guess. First, you need a wafer on which you can make a capacitor, which already means an SOI process, and SOI wafers. The lowest nodes with SOI available to mortals are 40nm, and 14nm on GlobalFoundries, but god knows how one gets GloFo to collaborate on that. Then, you need CMOS device which has enough thermal budget to survive both own, and DRAM creation. Third, I think on-die DRAM will only make sense when it wins over SRAM. DRAM cells cannot physically go smaller than the minimal size of a trench capacitor. I believe at 5-7nm nodes, 6T SRAM will already be smaller than a reasonably fast eDRAM per area. We know that IBM's Z15 is a 14nm FinFet chip, and it has DRAM on board, with them probably somehow doing DRAM first.
- MayeulC 5y agoI work on ferroelectric hafnium, which looks promising with regards to CMOS compatibility. It's non-volatile, though I guess you could also use it like DRAM. Endurance is an issue for now though (it's approaching RAM use-cases, but not SRAM yet). As you said, I'm not sure about the density part. Unless it's completely done in BEOL, I don't see designers trade precious chip real estate for memory (unless pin or power-limited, of course).
- baybal2 5y agoHafnium? Is it something FRAM related? What do you think on FRAM vs. next generation MRAM?
- MayeulC 5y agoI don't know much about STT-MRAM, so I'll avoid making a fool of myself. Looking more into the details is on my TODO. Look at the datasheets and make your choice, as usual. I am not sure how the situation will evolve on either side, my understanding is that FRAM could be more energy-efficient. Well, hafnium can be used to make ferroelectric crystals, that are necessary for ferroelectric memories (FRAM). The most used ferroelectric material is PZT, which has lead, and is a nightmare for CMOS compatibility due to contamination issues, and temperatures. It's a bit light on the details, but maybe I should point you towards the video that explains our project: https://www.youtube.com/watch?v=M8tL-nN7G-A https://www.youtube.com/watch?v=M8tL-nN7G-A The most exciting part might not be the performance (though it looks good), but the way ferroelectrics can be used for new circuits (variable treshold transistors thanks to FeFETs). Hafnium has been used in gate oxides for a few years now so it's quite compatible with CMOS.
- ksec 5y ago>https://www.tomshardware.com/news/innovative-type-of-memory-promises-higher-capacity-and-performance https://www.tomshardware.com/news/innovative-type-of-memory-... No word on latency though.