4 ms·
Latency is still unclear, and probably worse than L3.
by Scene_Cast2 5y ago
Latency is still unclear, and probably worse than L3.
- coreblocks 5y agoGoing over TSV will definitely incur at least one clock cycle.
- Dylan16807 5y agoIf you're on a high end chip then you already have to talk to the other chiplet for half your L3. A stacked chip should be a lot faster than that.
- ece 5y agoThe additional L3 is per chiplet, so you're still going to have to talk to other chiplets and their L3. Latency numbers would be good to see. This is definitely better than eDRAM L4 on the I/O die, and that's still something they could do, so props for that. The power cost will really determine if we see this in Laptops or not though.
- Dylan16807 5y ago> The additional L3 is per chiplet, so you're still going to have to talk to other chiplets and their L3. You will sometimes, but traffic that still overflows to the other chiplet is probably almost all traffic that would have gone to RAM before. And as a reference point, cross-chiplet L3 is about 50 nanoseconds slower than local L3. That will dwarf most things.