4 ms·

In isolation, this seems like a decent CPU, but I wonder if there is any benefit in using this over using a VexRiscv, which seems to cover the same spectrum as

In isolation, this seems like a decent CPU, but I wonder if there is any benefit in using this over using a VexRiscv, which seems to cover the same spectrum as this in terms of performance (from 2 to 5 pipeline stages) and features, yet requires less LUTs? This one supports the standard RISC-V debug extensions and doesn’t require a custom version of openocd, but is there anything else?

_quarks_ 5y ago
It is hard to compare two RISC-V cores if they do not have similar configuration options. For example: what kind of ISA extensions, supported traps, custom extensions, CSRs, etc. does VexRiscv "SmallAndProductive" configuration include? I like that it is written in VHDL and provides an all-in-one package: cpu, soc and software
- tverbeure 5y ago
  The SmallAndProductive configuration can be found here: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/GenSmallAndProductive.scala https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s.... It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all bypass paths included, so it executes straight code at 1 instruction per clock. The VexRiscv also comes with a bunch of full featured SOCs. The VexRiscv is configurable to the extreme and it’s extremely easy to do so. There are tons of other configurations in the same directory, from even smaller to full Linux SMP configs. It’d be trivial to create one that has the same configuration as this one and compare. SpinalHDL supports both Verilog and VHDL output, so you’re covered there as well. It’s not native VHDL, of course, so if you want to understand the code at the VHDL level instead of just wanting to use a soft core CPU, it’s probably not for you. Those who just need a CPU for a non-Scala environment (e.g. Litex) just pre-generate a whole bunch of configurations and then pick what they need for a certain use case. The VexRiscv design methodology is pretty amazing as well. I wrote about it here: https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CP....

_quarks_ 5y ago

It is hard to compare two RISC-V cores if they do not have similar configuration options. For example: what kind of ISA extensions, supported traps, custom extensions, CSRs, etc. does VexRiscv "SmallAndProductive" configuration include? I like that it is written in VHDL and provides an all-in-one package: cpu, soc and software

tverbeure 5y ago
The SmallAndProductive configuration can be found here: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/demo/GenSmallAndProductive.scala https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s.... It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all bypass paths included, so it executes straight code at 1 instruction per clock. The VexRiscv also comes with a bunch of full featured SOCs. The VexRiscv is configurable to the extreme and it’s extremely easy to do so. There are tons of other configurations in the same directory, from even smaller to full Linux SMP configs. It’d be trivial to create one that has the same configuration as this one and compare. SpinalHDL supports both Verilog and VHDL output, so you’re covered there as well. It’s not native VHDL, of course, so if you want to understand the code at the VHDL level instead of just wanting to use a soft core CPU, it’s probably not for you. Those who just need a CPU for a non-Scala environment (e.g. Litex) just pre-generate a whole bunch of configurations and then pick what they need for a certain use case. The VexRiscv design methodology is pretty amazing as well. I wrote about it here: https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CP....