11 ms·

RISC-V is amazing as what it is, but it isn't a competitor for high-end performance. It's simply not designed for that.

einpoklum 5y ago
Can you link to an explanation of why that is?
whazor 5y ago
RISC-V is ideal to build around a custom ASIC and could be used for high-end performance stuff, just very specific performance stuff.
s-macke 5y ago
RISC-V is first and foremost an instruction set architecture. Like all architectures it has a few weaknesses. But if you spend enough money, there is no reason for RISC-V not to be a competitor in the high-end performance segment.
solarkraft 5y ago
Yet? I know virtually nothing about the internals, but that‘s also what people said about ARM.
mhh__ 5y ago
If X86 still competes I see no reason why RISC-V can't also
- pjmlp 5y ago
  RISC-V doesn't have 40 years of ecosystem.
  - mhh__ 5y ago
    > but it isn't a competitor for high-end performance. It's simply not designed for that.
    - pjmlp 5y ago
      x86 owns most high-end performace systems, still fail to see the relation of the statement. > If X86 still competes I see no reason why RISC-V can't also First RISC-V needs to catch up with the 40 years of x86 improvements that kicked out SPARC, Cray, SGI and others from high-end performace systems.
      - mhh__ 5y ago
        What is RISC-V? It's an ISA not a microarchitecture. If you can make x86 fast you can make RISC-V fast
        toast0 5y ago
        Sure, you can make anything fast, but the question is will it take 40 years of a lot of work, and if so, where will x86 and ARM be when you get there? I'd suspect an ISA designed in the last few years with performance in mind (even if not a priority), wouldn't take as long to get to where the industry is now, but it's still a lot of years of focused effort required, and we'll see. I don't have a horse in the race, except that I do like my experience to not evaporate; and I sincerly hope real mode segmented address edge cases aren't something I'd need to relearn on another ISA even though they're still (barely) relevant on x86 in early boot.
        mhh__ 5y ago
        The point is that you can make it fast more easily. Decoding x86 instructions in parallel efficiently is taxing, whereas with ARM and RISC-V it's much more tractable for example. Saying X86 is 40 years work is also kind of stupid, as a huge amount of the ISA dead weight, and high performance implementations have their roots much earlier than that (e.g. Intel have tried to move on at least once and ended up coming back to the OOO superscalar paradigm).
        pjmlp 5y ago
        As stupid as it may be, it is 40 years of tooling, libraries and languages.
throwaway4good 5y ago
They could have gone for the license free instruction set of RISC-V + extensions instead of continueing to pay for ARM. Just shows the power of an establed ISA (all the software that runs on top of it) and how solid ARM's business model is.
- loup-vaillant 5y ago
  Something I don't understand here: do we really have to pay ARM for their instruction set? Does AMD pays Intel a fee for using x86? Does Intel pay AMD a fee for using their 64 bit extensions? Does anybody pay the inventor of the SSE and AVX instruction sets? Does anybody pays Nintendo for deploying emulators? The ISA is an interface, and as such may not be copyrightable or even patentable. Even if it was, we've had various interoperability exceptions, and one does need an ARM ISA to run a program compiled for ARM. Besides, as far as I know ARM doesn't just license the ISA. It licenses cores. There's a good chance that if you make your own cores to implement an ARM ISA, you wouldn't have to pay any fee. You may however have to get around trademark, and not call your CPUs "ARM CPUs". Though I suspect "ARM compatible" would work perfectly (just like "IBM compatible" worked with third party PC vendors).
  - dageshi 5y ago
    AMD did or does pay for an x86 license, I think to intel?
    - deleted 5y ago
      [deleted]
    - Pet_Ant 5y ago
      I believe the situation is that they both have relevant patents, especially since AMD went 64 bit, and so they cross-license to each other and call it even.
  - bluGill 5y ago
    Even if you don't have to legally, you want to because those license fees are how the money for the next ISA version are made. It is a prisoners delimma situation where nobody has defected.
audunw 5y ago
> It's simply not designed for that. I don't agree with that. The base ISA is highly optimised for high performance. Many of the decisions made are precisely because it makes it easier to design very wide superscalar CPUs. The vector extension is also looking like it'll be more efficient than ARMs. What's missing, is instruction set extensions that makes it comparable to ARM/x86 across all workloads. And obviously it's far less mature in general.
- adrian_b 5y ago
  Sorry, RISC-V is not a bad ISA, but saying that it "is highly optimised for high performance" is extremely far from the truth. RISC-V has been optimized for a single-purpose, being as simple as possible to be easily taught to students and implemented by them in a limited time. It lacks many features required for high performance without hardware of excessive complexity, the most obvious being that RISC-V does not have decent addressing modes, so that the highest performance implementation reported until now (by Alibaba at the 2020 Hot Chips Conference) had to add a non-standard ISA extension to correct this. Nobody remotely competent chooses RISC-V for "high performance" in any definition of that term. RISC-V can be the right choice in many cases because: 1. No costs for using the RISC-V ISA 2. Easy customization with non-standard extensions 3. An already existing complete software development environment, with compilers, debuggers etc. 4. Acceptable performance at a given implementation cost There is no need to invent extra fictitious advantages, like "high performance".
  - userbinator 5y ago
    In other words, it's basically closer to a replacement for MIPS, which is already everywhere in a lot of embedded devices (and arguably not "high performance" ones --- the cheapest tablets and smartphones use MIPS.)
    - snvzz 5y ago
      >it's basically closer to a replacement for MIPS It is actually a replacement for MIPS in a more literal sense: The company owning MIPS has recently renamed itself to MIPS, and it abandoned MIPS ISA in favor of RISC-V ISA.
nickik 5y ago
That's simply wrong. RISC-V is explicitly designed to enable high-end performance. That was literally one of their goals. Of course with the necessary extensions but that is the case on all ISA.
- tyingq 5y ago
  The original paper with the goals: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...
  - snvzz 5y ago
    Please also link the current version[0], so that people can see whether the goals have changed. [0] https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ (start with chapter 1 of the unprivileged spec)
snvzz 5y ago
This is a load of bull, and it can be readily dismissed after reading the first pace of the unprivileged spec[0]. As a practical counterexample to that FUD, it is also the ISA chosen by the Barcelona Super-computing Center EuroHPC[1] to design a new high performance CPU for future supercomputers. [0]https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ [1]https://www.bsc.es/news/bsc-news/bsc-working-towards-the-first-completely-open-source-european-full-stack-ecosystem-based-new-risc-v https://www.bsc.es/news/bsc-news/bsc-working-towards-the-fir...

Can you link to an explanation of why that is?

RISC-V is ideal to build around a custom ASIC and could be used for high-end performance stuff, just very specific performance stuff.

s-macke 5y ago

RISC-V is first and foremost an instruction set architecture. Like all architectures it has a few weaknesses. But if you spend enough money, there is no reason for RISC-V not to be a competitor in the high-end performance segment.

solarkraft 5y ago

Yet? I know virtually nothing about the internals, but that‘s also what people said about ARM.

mhh__ 5y ago

If X86 still competes I see no reason why RISC-V can't also

pjmlp 5y ago
RISC-V doesn't have 40 years of ecosystem.
- mhh__ 5y ago
  > but it isn't a competitor for high-end performance. It's simply not designed for that.
  - pjmlp 5y ago
    x86 owns most high-end performace systems, still fail to see the relation of the statement. > If X86 still competes I see no reason why RISC-V can't also First RISC-V needs to catch up with the 40 years of x86 improvements that kicked out SPARC, Cray, SGI and others from high-end performace systems.
    - mhh__ 5y ago
      What is RISC-V? It's an ISA not a microarchitecture. If you can make x86 fast you can make RISC-V fast
      - toast0 5y ago
        Sure, you can make anything fast, but the question is will it take 40 years of a lot of work, and if so, where will x86 and ARM be when you get there? I'd suspect an ISA designed in the last few years with performance in mind (even if not a priority), wouldn't take as long to get to where the industry is now, but it's still a lot of years of focused effort required, and we'll see. I don't have a horse in the race, except that I do like my experience to not evaporate; and I sincerly hope real mode segmented address edge cases aren't something I'd need to relearn on another ISA even though they're still (barely) relevant on x86 in early boot.
        mhh__ 5y ago
        The point is that you can make it fast more easily. Decoding x86 instructions in parallel efficiently is taxing, whereas with ARM and RISC-V it's much more tractable for example. Saying X86 is 40 years work is also kind of stupid, as a huge amount of the ISA dead weight, and high performance implementations have their roots much earlier than that (e.g. Intel have tried to move on at least once and ended up coming back to the OOO superscalar paradigm).
        pjmlp 5y ago
        As stupid as it may be, it is 40 years of tooling, libraries and languages.

throwaway4good 5y ago

They could have gone for the license free instruction set of RISC-V + extensions instead of continueing to pay for ARM. Just shows the power of an establed ISA (all the software that runs on top of it) and how solid ARM's business model is.

loup-vaillant 5y ago
Something I don't understand here: do we really have to pay ARM for their instruction set? Does AMD pays Intel a fee for using x86? Does Intel pay AMD a fee for using their 64 bit extensions? Does anybody pay the inventor of the SSE and AVX instruction sets? Does anybody pays Nintendo for deploying emulators? The ISA is an interface, and as such may not be copyrightable or even patentable. Even if it was, we've had various interoperability exceptions, and one does need an ARM ISA to run a program compiled for ARM. Besides, as far as I know ARM doesn't just license the ISA. It licenses cores. There's a good chance that if you make your own cores to implement an ARM ISA, you wouldn't have to pay any fee. You may however have to get around trademark, and not call your CPUs "ARM CPUs". Though I suspect "ARM compatible" would work perfectly (just like "IBM compatible" worked with third party PC vendors).
- dageshi 5y ago
  AMD did or does pay for an x86 license, I think to intel?
  - deleted 5y ago
    [deleted]
  - Pet_Ant 5y ago
    I believe the situation is that they both have relevant patents, especially since AMD went 64 bit, and so they cross-license to each other and call it even.
- bluGill 5y ago
  Even if you don't have to legally, you want to because those license fees are how the money for the next ISA version are made. It is a prisoners delimma situation where nobody has defected.

audunw 5y ago

> It's simply not designed for that. I don't agree with that. The base ISA is highly optimised for high performance. Many of the decisions made are precisely because it makes it easier to design very wide superscalar CPUs. The vector extension is also looking like it'll be more efficient than ARMs. What's missing, is instruction set extensions that makes it comparable to ARM/x86 across all workloads. And obviously it's far less mature in general.

adrian_b 5y ago
Sorry, RISC-V is not a bad ISA, but saying that it "is highly optimised for high performance" is extremely far from the truth. RISC-V has been optimized for a single-purpose, being as simple as possible to be easily taught to students and implemented by them in a limited time. It lacks many features required for high performance without hardware of excessive complexity, the most obvious being that RISC-V does not have decent addressing modes, so that the highest performance implementation reported until now (by Alibaba at the 2020 Hot Chips Conference) had to add a non-standard ISA extension to correct this. Nobody remotely competent chooses RISC-V for "high performance" in any definition of that term. RISC-V can be the right choice in many cases because: 1. No costs for using the RISC-V ISA 2. Easy customization with non-standard extensions 3. An already existing complete software development environment, with compilers, debuggers etc. 4. Acceptable performance at a given implementation cost There is no need to invent extra fictitious advantages, like "high performance".
- userbinator 5y ago
  In other words, it's basically closer to a replacement for MIPS, which is already everywhere in a lot of embedded devices (and arguably not "high performance" ones --- the cheapest tablets and smartphones use MIPS.)
  - snvzz 5y ago
    >it's basically closer to a replacement for MIPS It is actually a replacement for MIPS in a more literal sense: The company owning MIPS has recently renamed itself to MIPS, and it abandoned MIPS ISA in favor of RISC-V ISA.

nickik 5y ago

That's simply wrong. RISC-V is explicitly designed to enable high-end performance. That was literally one of their goals. Of course with the necessary extensions but that is the case on all ISA.

tyingq 5y ago
The original paper with the goals: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-62.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-...
- snvzz 5y ago
  Please also link the current version[0], so that people can see whether the goals have changed. [0] https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ (start with chapter 1 of the unprivileged spec)

snvzz 5y ago

This is a load of bull, and it can be readily dismissed after reading the first pace of the unprivileged spec[0]. As a practical counterexample to that FUD, it is also the ISA chosen by the Barcelona Super-computing Center EuroHPC[1] to design a new high performance CPU for future supercomputers. [0]https://riscv.org/technical/specifications/ https://riscv.org/technical/specifications/ [1]https://www.bsc.es/news/bsc-news/bsc-working-towards-the-first-completely-open-source-european-full-stack-ecosystem-based-new-risc-v https://www.bsc.es/news/bsc-news/bsc-working-towards-the-fir...