3 ms·

Some saw/earnt vhdl someone after it emerged. ~half? Verilog had a popularity ramp up time of a few years too. I'm going with a much smaller number than you the

by harry8 6y ago

Some saw/earnt vhdl someone after it emerged. ~half? Verilog had a popularity ramp up time of a few years too. I'm going with a much smaller number than you there. Could be way wrong!

pjmlp 6y ago
VHDL/Verilog is a bit like Pascal/C division used to be, with VHDL having more fans in Europe and Verilog on US, and then the respective countries that do business with them. At least that is how I understand the market division, it might also be that one of them has already won, not sure about that.
- RugnirViking 6y ago
  Can confirm was taught vhdl in my robotics master's degree this year, studying in Europe
- harry8 6y ago
  I decided to learn Verilog after reading of a different division. Namely that VHDL is the preferred option of defense industry applications in the US, Verilog preferred in non-MIC business. Given the advantages of VHDL over Verilog looked less than overwhelming and Verilog has some advantages of its own, (verilator, seemingly more RISC-V cores in verilog, open-source tool chain looks closer to being useful to me etc.) That's the call I made. It looks like it's not so hard to switch from one to the other if you need to do that though.
themulticaster 6y ago
I think the apparent increase in Verilog popularity is due to pretty much all FOSS toolchains (i.e. mostly Yosys) only supporting Verilog [1], so most of the content publicly visible on blogs etc. uses Verilog. And I guess the reason that most tooling focuses on Verilog is that the VHDL standard is a little bit of a mess from a parsing point of view. Essentially, in order to correctly parse some VHDL file A you first need to parse every other file that A might depend on. [2] Source: Tried writing a VHDL parser a few years ago. [1] AFAIK you can buy a license for a VHDL frontend from one of the companies contributing to Yosys, but that's a different story. [2] Example: What is f(1)? It could be a) calling a function called f with a parameter_association_list consisting of 1 or b) an indexed name, accessing an array called f at index 1, or c) some other things if we're not currently in an expression context. The only way to parse this correctly is to know what f is, but if f is not defined in the file you're currently parsing, there's no way to know other than parsing all other files...

by harry8 6y ago

Some saw/earnt vhdl someone after it emerged. ~half? Verilog had a popularity ramp up time of a few years too. I'm going with a much smaller number than you there. Could be way wrong!

pjmlp 6y ago

VHDL/Verilog is a bit like Pascal/C division used to be, with VHDL having more fans in Europe and Verilog on US, and then the respective countries that do business with them. At least that is how I understand the market division, it might also be that one of them has already won, not sure about that.

RugnirViking 6y ago
Can confirm was taught vhdl in my robotics master's degree this year, studying in Europe
harry8 6y ago
I decided to learn Verilog after reading of a different division. Namely that VHDL is the preferred option of defense industry applications in the US, Verilog preferred in non-MIC business. Given the advantages of VHDL over Verilog looked less than overwhelming and Verilog has some advantages of its own, (verilator, seemingly more RISC-V cores in verilog, open-source tool chain looks closer to being useful to me etc.) That's the call I made. It looks like it's not so hard to switch from one to the other if you need to do that though.

themulticaster 6y ago

I think the apparent increase in Verilog popularity is due to pretty much all FOSS toolchains (i.e. mostly Yosys) only supporting Verilog [1], so most of the content publicly visible on blogs etc. uses Verilog. And I guess the reason that most tooling focuses on Verilog is that the VHDL standard is a little bit of a mess from a parsing point of view. Essentially, in order to correctly parse some VHDL file A you first need to parse every other file that A might depend on. [2] Source: Tried writing a VHDL parser a few years ago. [1] AFAIK you can buy a license for a VHDL frontend from one of the companies contributing to Yosys, but that's a different story. [2] Example: What is f(1)? It could be a) calling a function called f with a parameter_association_list consisting of 1 or b) an indexed name, accessing an array called f at index 1, or c) some other things if we're not currently in an expression context. The only way to parse this correctly is to know what f is, but if f is not defined in the file you're currently parsing, there's no way to know other than parsing all other files...