4 ms·

I would bet it's less than 10,000 in the entire world.

userbinator 6y ago
This feels a bit like that classic estimation interview question... Verilog originated in 1984 and educational institutions have been teaching it roughly as long, multiply by how many students graduate each year in an EE-related field and I'm pretty sure the number is far more than that in India alone. Of course, the number of people who know Verilog (and Factorio) enough to implement something like this is going to be a fraction of that.
- jakear 6y ago
  Sure, but there’s a difference between “had a couple courses using it in college” and “have an understanding of the language sufficient to develop a novel backend”.
  - devit 6y ago
    You don't need much understanding in advance to develop a novel backend, since you are forced and guided to learn the whole language as you try to write the backend and start pattern matching on the data structures.
  - themulticaster 6y ago
    This project actually uses Yosys. From a quick glance at the code, this tool essentially uses Yosys for the heavy-duty logic stuff [1], resulting in a JSON-based logic definition using a couple of standard cells (DFF, MUX, arithmetic, etc.) that verilog2factorio parses [2] and translates into predefined Factorio blueprints. The only part that I couldn't find would be laying out the cells into the overall blueprint (and performing routing). [1] https://github.com/Redcrafter/verilog2factorio/blob/9691b7025a6b023ffaa82a1393ed8dfe8adeb10e/src/main.ts#L11-L12 https://github.com/Redcrafter/verilog2factorio/blob/9691b702... [2] https://github.com/Redcrafter/verilog2factorio/blob/9691b7025a6b023ffaa82a1393ed8dfe8adeb10e/src/parser.ts https://github.com/Redcrafter/verilog2factorio/blob/9691b702...
    - linux_is_nice 6y ago
      It does simulated annealing in src/sim.ts, I think.
- ummonk 6y ago
  I don't consider "took a class in it" sufficient to constitute "really understand" in most subjects. Classes often don't actually teach actual understanding of the subject, and even when they do, most people end up forgetting it afterwards.
- harry8 6y ago
  Some saw/earnt vhdl someone after it emerged. ~half? Verilog had a popularity ramp up time of a few years too. I'm going with a much smaller number than you there. Could be way wrong!
  - pjmlp 6y ago
    VHDL/Verilog is a bit like Pascal/C division used to be, with VHDL having more fans in Europe and Verilog on US, and then the respective countries that do business with them. At least that is how I understand the market division, it might also be that one of them has already won, not sure about that.
    - RugnirViking 6y ago
      Can confirm was taught vhdl in my robotics master's degree this year, studying in Europe
    - harry8 6y ago
      I decided to learn Verilog after reading of a different division. Namely that VHDL is the preferred option of defense industry applications in the US, Verilog preferred in non-MIC business. Given the advantages of VHDL over Verilog looked less than overwhelming and Verilog has some advantages of its own, (verilator, seemingly more RISC-V cores in verilog, open-source tool chain looks closer to being useful to me etc.) That's the call I made. It looks like it's not so hard to switch from one to the other if you need to do that though.
  - themulticaster 6y ago
    I think the apparent increase in Verilog popularity is due to pretty much all FOSS toolchains (i.e. mostly Yosys) only supporting Verilog [1], so most of the content publicly visible on blogs etc. uses Verilog. And I guess the reason that most tooling focuses on Verilog is that the VHDL standard is a little bit of a mess from a parsing point of view. Essentially, in order to correctly parse some VHDL file A you first need to parse every other file that A might depend on. [2] Source: Tried writing a VHDL parser a few years ago. [1] AFAIK you can buy a license for a VHDL frontend from one of the companies contributing to Yosys, but that's a different story. [2] Example: What is f(1)? It could be a) calling a function called f with a parameter_association_list consisting of 1 or b) an indexed name, accessing an array called f at index 1, or c) some other things if we're not currently in an expression context. The only way to parse this correctly is to know what f is, but if f is not defined in the file you're currently parsing, there's no way to know other than parsing all other files...

This feels a bit like that classic estimation interview question... Verilog originated in 1984 and educational institutions have been teaching it roughly as long, multiply by how many students graduate each year in an EE-related field and I'm pretty sure the number is far more than that in India alone. Of course, the number of people who know Verilog (and Factorio) enough to implement something like this is going to be a fraction of that.

jakear 6y ago
Sure, but there’s a difference between “had a couple courses using it in college” and “have an understanding of the language sufficient to develop a novel backend”.
- devit 6y ago
  You don't need much understanding in advance to develop a novel backend, since you are forced and guided to learn the whole language as you try to write the backend and start pattern matching on the data structures.
- themulticaster 6y ago
  This project actually uses Yosys. From a quick glance at the code, this tool essentially uses Yosys for the heavy-duty logic stuff [1], resulting in a JSON-based logic definition using a couple of standard cells (DFF, MUX, arithmetic, etc.) that verilog2factorio parses [2] and translates into predefined Factorio blueprints. The only part that I couldn't find would be laying out the cells into the overall blueprint (and performing routing). [1] https://github.com/Redcrafter/verilog2factorio/blob/9691b7025a6b023ffaa82a1393ed8dfe8adeb10e/src/main.ts#L11-L12 https://github.com/Redcrafter/verilog2factorio/blob/9691b702... [2] https://github.com/Redcrafter/verilog2factorio/blob/9691b7025a6b023ffaa82a1393ed8dfe8adeb10e/src/parser.ts https://github.com/Redcrafter/verilog2factorio/blob/9691b702...
  - linux_is_nice 6y ago
    It does simulated annealing in src/sim.ts, I think.
ummonk 6y ago
I don't consider "took a class in it" sufficient to constitute "really understand" in most subjects. Classes often don't actually teach actual understanding of the subject, and even when they do, most people end up forgetting it afterwards.
harry8 6y ago
Some saw/earnt vhdl someone after it emerged. ~half? Verilog had a popularity ramp up time of a few years too. I'm going with a much smaller number than you there. Could be way wrong!
- pjmlp 6y ago
  VHDL/Verilog is a bit like Pascal/C division used to be, with VHDL having more fans in Europe and Verilog on US, and then the respective countries that do business with them. At least that is how I understand the market division, it might also be that one of them has already won, not sure about that.
  - RugnirViking 6y ago
    Can confirm was taught vhdl in my robotics master's degree this year, studying in Europe
  - harry8 6y ago
    I decided to learn Verilog after reading of a different division. Namely that VHDL is the preferred option of defense industry applications in the US, Verilog preferred in non-MIC business. Given the advantages of VHDL over Verilog looked less than overwhelming and Verilog has some advantages of its own, (verilator, seemingly more RISC-V cores in verilog, open-source tool chain looks closer to being useful to me etc.) That's the call I made. It looks like it's not so hard to switch from one to the other if you need to do that though.
- themulticaster 6y ago
  I think the apparent increase in Verilog popularity is due to pretty much all FOSS toolchains (i.e. mostly Yosys) only supporting Verilog [1], so most of the content publicly visible on blogs etc. uses Verilog. And I guess the reason that most tooling focuses on Verilog is that the VHDL standard is a little bit of a mess from a parsing point of view. Essentially, in order to correctly parse some VHDL file A you first need to parse every other file that A might depend on. [2] Source: Tried writing a VHDL parser a few years ago. [1] AFAIK you can buy a license for a VHDL frontend from one of the companies contributing to Yosys, but that's a different story. [2] Example: What is f(1)? It could be a) calling a function called f with a parameter_association_list consisting of 1 or b) an indexed name, accessing an array called f at index 1, or c) some other things if we're not currently in an expression context. The only way to parse this correctly is to know what f is, but if f is not defined in the file you're currently parsing, there's no way to know other than parsing all other files...