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J2 open processor: an open source processor using the SuperH ISA
- jsnell 6y agoPreviously on HN: https://news.ycombinator.com/item?id=12105913 https://news.ycombinator.com/item?id=12105913 https://news.ycombinator.com/item?id=20658584 https://news.ycombinator.com/item?id=20658584 Is the project still alive? There's no news for over 4 years.
- rdpintqogeogsaa 6y agoThe mailing list[0] has been trucking along. Not with a lot of force, but at least one post per month. [0] https://lists.j-core.org/pipermail/j-core/ https://lists.j-core.org/pipermail/j-core/
- cbmuser 6y agoYes, the first Turtle Boards have been delivered and kernel support on SH has been improving here and there. I‘m Debian‘s sh4 maintainer and I have done quite a lot to keep the port alive and improve it.
- MaxBarraclough 6y ago> I‘m Debian‘s sh4 maintainer and I have done quite a lot to keep the port alive and improve it. Neat! What's your reason for doing this? Just a fan of retro architectures, or something else?
- cbmuser 6y agoJust for fun and for educational purposes. I‘m maintaining most unofficial architectures in Debian that are part of „Debian Ports“.
- sitkack 6y agoYou should do an AMA. What does that entail? What skillset does one need? How do you connect with your users? The ones with the weird hardware?
- pantalaimon 6y agoNice! Are there still plans for J3/J4?
- deleted 6y ago[deleted]
- cbmuser 6y agoThe J-Core people are planning to release a J4 CPU, but I don’t know when that will happen. I just received my Turtle Board with J2 and will give it a go how far I will get with that.
- freemint 6y agoI'm in contact with the company which open sourced the J-Core family and of processors. They have much in the pipeline they want to open source. However they just haven't found the time to open source the next stuff since they need to clean it up before release and don't just want to occasionally dump a tarbal but provide a full versioned history of their repository.
- peter_d_sherman 6y ago>The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt. >Numato: The cheapest usable FPGA development board ($50 US) the j2 build system currently targets is the Numato Mimas v2 (also available on amazon). It contains a Xlinux "Spartan 6" LX9 FPGA that can run a J2 at 50mhz, 64 megs of SDRAM, USB2 mini-B, and a micro-sd card slot. PDS: Nice! But, it would be an additional serious "would be nice"(!) -- if this could run on Lattice FPGA's / IceStorm Open Source Toolchain: https://www.latticesemi.com/Products https://www.latticesemi.com/Products http://www.clifford.at/icestorm/ http://www.clifford.at/icestorm/ https://github.com/YosysHQ/icestorm https://github.com/YosysHQ/icestorm
- freemint 6y agoYou might be interested in https://github.com/j-core/jcore-j1-ghdl https://github.com/j-core/jcore-j1-ghdl
- alexhutcheson 6y agoI think https://github.com/j-core/j-core-ice40 https://github.com/j-core/j-core-ice40 is the better repo to check out.
- freemint 6y agoactually yes.
- zdw 6y agoThere's some activity in the FPGA retrogaming emulation community about the Sega Saturn and other consoles that use the SH2, along with FPGA reimplementations of the graphics chips: https://twitter.com/srg320_/status/1363880878263443457 https://twitter.com/srg320_/status/1363880878263443457 I wonder if this is the CPU core that's being used.
- freemint 6y agoThe Sega Saturn is not an good target to emulate as a lot of code relies on cycle perfect due the lack of locking between the two cores. The J2 has different cycle times from the SH2 used in the Saturn. Since the J2 is quiet modular it might be possible to modify the timings but i somewhat doubtful that 2 vector units and two cores will fit on an affordable for hobbyist FPGA but i honestly don't know. Edit: Changed DreamCast -> Saturn
- monocasa 6y agoThat's interesting about the different cycle times given that SH2 is probably one of the most pure 'one instruction per cycle' RISCs out there, even breaking apart the iterative divide into each cycle's operation. Is there any chance you can expand on the issues there?
- freemint 6y agoI would have to ask or rewatch all J-Core talks. I recall something like that: "We traded die space for speed so one instruction which takes one cycle on an SH takes 2 on J-Core." If you are really interested i can see if i can come back to you.
- JohnBooty 6y agoThe Saturn has a complex array of custom chips, including a second SH2, two graphics chips, a DSP, etc. All sharing access to various resources such as memory. https://www.copetti.org/writings/consoles/sega-saturn/ https://www.copetti.org/writings/consoles/sega-saturn/ So, it's notoriously difficult to code for (if you want peak performance) and tough to emulate. I think each individual core is easy to emulate, but the whole salad of chips is another story. Coding Secrets on YouTube has some videos on writing code for the Saturn, like this one. Not SH2 specific, but wow. https://www.youtube.com/watch?v=czqwd43WQWM https://www.youtube.com/watch?v=czqwd43WQWM https://www.youtube.com/watch?v=wU2UoxLtIm8 https://www.youtube.com/watch?v=wU2UoxLtIm8 (mentions the incomplete documentation from Sega, as if the system wasn't complicated enough without iffy documentation as well)
- yjftsjthsd-h 6y agoSo this feels like it begs the question: What's the big deal with RISC-V if this exists? If we've had a Linux-capable BSD-licensed patent-free processor since 2015, why did we spend so much time and effort and money to make another completely new ISA?
- chasil 6y agoNotice that it does not implement an MMU, nor was 64-bit ever implemented in the instruction set.
- yjftsjthsd-h 6y ago> J2 is a nommu processor because sh2 (the processor in the Sega Saturn game console) was, and the last sh2 patent expired in October 2014. The sh4 processor (dreamcast) has an mmu, but the last sh4 patents don't exire until 2016. (Update: we're probably implementing a simpler MMU design which will run the same userspace software but require kernel and QEMU updates, which we'll submit upstream when ready.) Seems like it was in the pipeline, and still should be easier to add an MMU to a fully-fleshed system than create a whole new ISA. For that matter, there are plenty of RISC-V implementations without MMUs, aren't there? So they should be exactly the same. The 64-bit thing I'll give you, although it isn't obvious to me how much that would matter for most places where people are using ARM or RISC-V so far; it limits you to 4G of memory, but in embedded uses (phones, routers, raspberry pi) who cares?
- freemint 6y agoThey started before RISC-V existed. The reason why they build their own implementation of an CPU and not used some open Mips or Sparc is that they found that those used to much BUS bandwidth for their use case. SuperH was really well designed architecture with really good instruction set density. Instruction set density is not a thing tagged on to a spec which many cores don't implement and if it is implemented you end up having a mess of mixed 32 and 16 bit instructions. SuperH is cleaner in that everything is a 16 bit instruction which helps with making decoder cheaper.
- dleslie 6y ago> SH2 made it to the United states in the Sega Saturn game console, and SH4 powered the Sega Dreamcast. And the 32X used the SH2!
- ulzeraj 6y agoSome versions of the HP Jornada handheld had an SH3 Hitashi processor. I remember running running JLime Linux on a 690e. The Linux system had to be installed on a CF card along with a binary that would kill Windows CE and boot the Linux kernel.
- antattack 6y agoIs it possible to predict of SuperH performance per Watt compared to Risc-V or ARM? It seems to be a great candidate for IoT CPUs.
- pjscott 6y agoSuperH and RISC-V and ARM are instruction sets, not microprocessors. The performance per Watt depends on the specific microprocessor architecture, the physical manufacturing technology, etc., much more than the instruction set.
- antattack 6y agoThanks. I assumed that ISA influences architecture more because there are ARM IoT processors but not X86.
- klelatti 6y agoI think that it's actually not an unreasonable question and the prior answer was a little short! For example ARM has different ISAs depending on the application: A for more complex Application processors, R for Realtime and M for Microcontroller. The ISA for M is less complex, less complex to implement and likely to use less power than A (or than a full x86 implementation). Not an expert but from what I've seen Super-H seems like a good candidate for a low power applications.
- freemint 6y agoThere definitely is an influence but the margin of ISA on power consumption are much smaller than what differentiation inside an ISA using engineering allows for. An ULTRASPARC with a huger register window is never going to be powesaving compared to an Atom but an i9 thread can eat more than an ULTRASPARC II as Intel is currently keen on showing.
- userbinator 6y agobecause there are ARM IoT processors but not X86. Intel did try... https://en.wikipedia.org/wiki/Intel_Quark https://en.wikipedia.org/wiki/Intel_Quark
- deleted 6y ago[deleted]
- mikepurvis 6y agoThe predecessor to the SuperH is the H8 family of devices, which notably included H8/3292, the microcontroller in the Lego Mindstorms RCX. Obviously an irrelevant implementation detail to 99% of users, but deeply important if you were one of those weirdos who compiled BrickOS for your system so that your Lego robot could run a real C program, and even moreso if you needed to rewrite parts of your program in native assembly language to make it run fast enough to be usable. (This was me, in my bedroom at age 16, furiously preparing a robot capable of playing Connect-4 for an rtlToronto Lego robotics competition called Deep Yellow...)
- userbinator 6y agoThe H8 or H8S is also used in many Thinkpads as the embedded controller: https://www.thinkwiki.org/wiki/Embedded_Controller_Chips https://www.thinkwiki.org/wiki/Embedded_Controller_Chips