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I don’t really know much about game emulation so I was curious about what differentiates this FPGA game project vs traditional CPU emulation. From their github

I don’t really know much about game emulation so I was curious about what differentiates this FPGA game project vs traditional CPU emulation. From their github page [1]: >Traditional emulators on CPUs execute code sequentially. This is a tricky method of emulation because real hardware has many chips and all of them work in parallel...This requires a lot of CPU power to emulate even an old and slow retro computer. Sometimes even a modern CPU working at 100 times the speed of the retro computer is not enough, so the emulator has to use approximation, skip emulation of some less important parts, or assume some standard work of the emulated system without extraordinary usage. > FPGA doesn't need high frequencies to emulate retro computers; it works at much lower frequencies than traditional emulators require. Since everything in FPGA works in parallel, it is no problem to handle any possible usage of the emulated system. [1] https://github.com/MiSTer-devel/Main_MiSTer/wiki/Why-FPGA https://github.com/MiSTer-devel/Main_MiSTer/wiki/Why-FPGA (Edited for formatting)

TillE 6y ago
byuu wrote a good article about this, unfortunately it's no longer available, but basically it should be self-evident that there's nothing inherently more accurate about hardware emulation. If you've actually decapped the original chips and duplicated them exactly in an FPGA, that's pretty cool. But otherwise it's just another approximation. The lower power requirements are nice, of course.
- mbalyuzi 6y ago
  Actually decapping the original chips is very much a thing. See for example Chris Smith's work mapping out the innards of the ZX Spectrum ULA - http://www.zxdesign.info/book/insideULA.shtml http://www.zxdesign.info/book/insideULA.shtml .
  - near 6y ago
    It is, but these cores are almost exclusively not being done that way. Not yet at least. I hope that they will be, that would be really awesome. I paid $1200 last year for the SNES PPUs to be decapped for this purpose, but it's a truly enormous undertaking to map out those chips and then recreate it in Verilog. You're talking thousands of hours of work per chip. If anyone reading this is able to help with that effort, please do let me know, we could really use the help.
    - FPGAhacker 6y ago
      Not that this is necessarily helpful to you in the short term, but it strikes me as a good problem for machine learning (going from die pictures to transistor schematic.)
    - tediousdemise 6y ago
      By decapped, do you mean delidded? Theoretically it would be possible to automate this with a couple things: - USB electron microscope to image the transistor topology - CV lib to identify connections and generate corresponding Verilog code
      - klodolph 6y ago
        “Decapping” is a more intense version of delidding where you use chemical agents or something similarly extreme (laser, plasma, milling) to remove the package (ceramic, plastic). My understanding is that there are people who do it often enough that it is automated in the way you describe, but you still need someone with a lot of skill to spend serious time on it. Computer vision works wonders but there are errors which must be identified and fixed. A lot of the chips people care about are can just be done optically, no electron microscope needed.
        tediousdemise 6y ago
        Ah, that’s a good distinction. I’d be pretty scared of damaging the hardware by doing that, but I’m sure there are some really experienced folks out there that would appreciate the hardware donation.
        klodolph 6y ago
        Decapping destroys the hardware.
- bcrl 6y ago
  That's exactly what's happening. There are loads of projects going on right now decapping old chips and reverse engineering them. From old CPUs like the 6502 to the Amiga Alice chip. It's just a matter of time before most of the retro systems are fully reverse engineered and documented.
  - deelowe 6y ago
    That's generally not what's happening with the mister cores. I haven't looked at all of them, but the ones I have studied are very high level in implementation.
    - foldor 6y ago
      To the best of my knowledge, the Neo Geo core has certain chips based on a full decap and implementation in FPGA. Not the entire system though.
      - deelowe 6y ago
        Neat. I'll have to look at that one.
  - astrange 6y ago
    FPGA cores are based on CPU emulators, so they aren't more accurate than the emulator, and decapping a chip doesn't help. FPGAs are written in languages like Verilog that are still high-level and do some probably misguided tricks to make it look like you're programming them with a vaguely C syntax.
    - deleted 6y ago
      [deleted]
    - pjc50 6y ago
      > FPGAs are written in languages like Verilog that are still high-level and do some probably misguided tricks to make it look like you're programming them with a vaguely C syntax. This is either incredibly badly explained or wrong. Verilog compiles to gate level.
- tediousdemise 6y ago
  On FPGAs (depending on the hardware mapping), you get the benefit of lower latency. I consider this to be timing accuracy. Say you have two implementations of an LED controlled by a switch: one which uses an FPGA and one which uses a microcontroller. The uC implementation must continuously poll peripherals connected to its GPIO pins at a set frequency; it must check the state of the switch, and then change the state of the LED. The FPGA, on the other hand, physically wires the switch to the LED; there is no lag when the state of the switch changes. The FPGA implementation can be scaled to connect however many additional lights and switches you want (limited by the size of the fabric), with zero overhead lag. This is the parallelization benefit of FPGAs that you may hear about. For the uC implementation, you must add additional switches and lights to the polling loop, which brings down performance in linear time, O(n). This is the drawback of sequential processing.
  - klodolph 6y ago
    Most game consoles don’t do any of this, though. The gamepad is polled by software. On the NES and SNES, the buttons are connected to a shift register (e.g. 4021). The CPU triggers a latch and then reads out the shift register one bit at a time.
    - djmips 6y ago
      This was given as an example, not for you to straw man about the gamepad.
      - klodolph 6y ago
        Don’t know what you’re getting at. You seem to have taken offense, and I think it’s because you misinterpreted what I wrote.
        kbenson 6y ago
        Your comment seemed to be positioned as a refutation of the prior comment (it could have been meant as an aside, but without something to indicate that it can be hard not to assume it's a counter). Unfortunately, if it was meant as a counter to the prior argument, countering just the example put forth does not actually address the argument put forth, so it it looks like a straw man argument itself (that is, addressing an example, even if it was presented by others, without making any attempt to address the position itself).
- zokier 6y ago
  I think big differentiator is that it is easier to get predictable latencies with FPGA where you control almost everything, compared to general-purpose PC which is not really that well optimized for hard real-time operation. So I believe "race the beam" style things are more easily accomplished with FPGAs, and also having tight audio-video sync. Although the PC emulation scene has been also doing some fairly incredible things too.
- emodendroket 6y ago
  That's true, but I think it's also true that you could trim a bit more lag if you do it well.
- valec 6y ago
  you can find it here https://archive.is/fWosI https://archive.is/fWosI
- tyingq 6y ago
  Quite a few of the FPGA soft cores related to 8 bit gaming are reverse engineered from either schematics, decapped chips, or both. Or they take pains to at least use the same number of cycles for each instruction, access SRAM or DRAM in the same way, etc.
- inDigiNeous 6y ago
  Unless you have seen MISTer running (especially on an fixed HZ old school CRT monitor) vs running that same thing emulated on on a modern cycle-exact emulator. The difference is really noticeable. This might come down to the emulator also running on a modern OS, which cannot guarantee at all times smooth framerates, whereas a dedicated FPGA can promise you that it's not running much more than the actual core needed to emulate that system. Especially on a 50/60Hz CRT monitor the difference and latency from the controller to pixels to screen is noticeably faster and stuff like scrolling the screen and sprites are buttery smooth, just like in the original hardware.
  - pozdnyshev 6y ago
    I would beg to differ. In fact, I would doubt many people could tell it apart in a blind test situation, especially on NES or SNES games. FPGA is just another expensive toy for hobbyists.
rtkwe 6y ago
There was a good article from Arstechnica a decade ago that pointed out why you need so much more power to get perfect emulation. To get exact emulation takes a lot of power because there are a few games which use odd tricks that are hard to document and precisely reimplement in software. FPGA emulation gets around that by more directly emulating the hardware. https://arstechnica.com/gaming/2011/08/accuracy-takes-power-one-mans-3ghz-quest-to-build-a-perfect-snes-emulator/ https://arstechnica.com/gaming/2011/08/accuracy-takes-power-...

TillE 6y ago

byuu wrote a good article about this, unfortunately it's no longer available, but basically it should be self-evident that there's nothing inherently more accurate about hardware emulation. If you've actually decapped the original chips and duplicated them exactly in an FPGA, that's pretty cool. But otherwise it's just another approximation. The lower power requirements are nice, of course.

mbalyuzi 6y ago
Actually decapping the original chips is very much a thing. See for example Chris Smith's work mapping out the innards of the ZX Spectrum ULA - http://www.zxdesign.info/book/insideULA.shtml http://www.zxdesign.info/book/insideULA.shtml .
- near 6y ago
  It is, but these cores are almost exclusively not being done that way. Not yet at least. I hope that they will be, that would be really awesome. I paid $1200 last year for the SNES PPUs to be decapped for this purpose, but it's a truly enormous undertaking to map out those chips and then recreate it in Verilog. You're talking thousands of hours of work per chip. If anyone reading this is able to help with that effort, please do let me know, we could really use the help.
  - FPGAhacker 6y ago
    Not that this is necessarily helpful to you in the short term, but it strikes me as a good problem for machine learning (going from die pictures to transistor schematic.)
  - tediousdemise 6y ago
    By decapped, do you mean delidded? Theoretically it would be possible to automate this with a couple things: - USB electron microscope to image the transistor topology - CV lib to identify connections and generate corresponding Verilog code
    - klodolph 6y ago
      “Decapping” is a more intense version of delidding where you use chemical agents or something similarly extreme (laser, plasma, milling) to remove the package (ceramic, plastic). My understanding is that there are people who do it often enough that it is automated in the way you describe, but you still need someone with a lot of skill to spend serious time on it. Computer vision works wonders but there are errors which must be identified and fixed. A lot of the chips people care about are can just be done optically, no electron microscope needed.
      - tediousdemise 6y ago
        Ah, that’s a good distinction. I’d be pretty scared of damaging the hardware by doing that, but I’m sure there are some really experienced folks out there that would appreciate the hardware donation.
        klodolph 6y ago
        Decapping destroys the hardware.
bcrl 6y ago
That's exactly what's happening. There are loads of projects going on right now decapping old chips and reverse engineering them. From old CPUs like the 6502 to the Amiga Alice chip. It's just a matter of time before most of the retro systems are fully reverse engineered and documented.
- deelowe 6y ago
  That's generally not what's happening with the mister cores. I haven't looked at all of them, but the ones I have studied are very high level in implementation.
  - foldor 6y ago
    To the best of my knowledge, the Neo Geo core has certain chips based on a full decap and implementation in FPGA. Not the entire system though.
    - deelowe 6y ago
      Neat. I'll have to look at that one.
- astrange 6y ago
  FPGA cores are based on CPU emulators, so they aren't more accurate than the emulator, and decapping a chip doesn't help. FPGAs are written in languages like Verilog that are still high-level and do some probably misguided tricks to make it look like you're programming them with a vaguely C syntax.
  - deleted 6y ago
    [deleted]
  - pjc50 6y ago
    > FPGAs are written in languages like Verilog that are still high-level and do some probably misguided tricks to make it look like you're programming them with a vaguely C syntax. This is either incredibly badly explained or wrong. Verilog compiles to gate level.
tediousdemise 6y ago
On FPGAs (depending on the hardware mapping), you get the benefit of lower latency. I consider this to be timing accuracy. Say you have two implementations of an LED controlled by a switch: one which uses an FPGA and one which uses a microcontroller. The uC implementation must continuously poll peripherals connected to its GPIO pins at a set frequency; it must check the state of the switch, and then change the state of the LED. The FPGA, on the other hand, physically wires the switch to the LED; there is no lag when the state of the switch changes. The FPGA implementation can be scaled to connect however many additional lights and switches you want (limited by the size of the fabric), with zero overhead lag. This is the parallelization benefit of FPGAs that you may hear about. For the uC implementation, you must add additional switches and lights to the polling loop, which brings down performance in linear time, O(n). This is the drawback of sequential processing.
- klodolph 6y ago
  Most game consoles don’t do any of this, though. The gamepad is polled by software. On the NES and SNES, the buttons are connected to a shift register (e.g. 4021). The CPU triggers a latch and then reads out the shift register one bit at a time.
  - djmips 6y ago
    This was given as an example, not for you to straw man about the gamepad.
    - klodolph 6y ago
      Don’t know what you’re getting at. You seem to have taken offense, and I think it’s because you misinterpreted what I wrote.
      - kbenson 6y ago
        Your comment seemed to be positioned as a refutation of the prior comment (it could have been meant as an aside, but without something to indicate that it can be hard not to assume it's a counter). Unfortunately, if it was meant as a counter to the prior argument, countering just the example put forth does not actually address the argument put forth, so it it looks like a straw man argument itself (that is, addressing an example, even if it was presented by others, without making any attempt to address the position itself).
zokier 6y ago
I think big differentiator is that it is easier to get predictable latencies with FPGA where you control almost everything, compared to general-purpose PC which is not really that well optimized for hard real-time operation. So I believe "race the beam" style things are more easily accomplished with FPGAs, and also having tight audio-video sync. Although the PC emulation scene has been also doing some fairly incredible things too.
emodendroket 6y ago
That's true, but I think it's also true that you could trim a bit more lag if you do it well.
valec 6y ago
you can find it here https://archive.is/fWosI https://archive.is/fWosI
tyingq 6y ago
Quite a few of the FPGA soft cores related to 8 bit gaming are reverse engineered from either schematics, decapped chips, or both. Or they take pains to at least use the same number of cycles for each instruction, access SRAM or DRAM in the same way, etc.
inDigiNeous 6y ago
Unless you have seen MISTer running (especially on an fixed HZ old school CRT monitor) vs running that same thing emulated on on a modern cycle-exact emulator. The difference is really noticeable. This might come down to the emulator also running on a modern OS, which cannot guarantee at all times smooth framerates, whereas a dedicated FPGA can promise you that it's not running much more than the actual core needed to emulate that system. Especially on a 50/60Hz CRT monitor the difference and latency from the controller to pixels to screen is noticeably faster and stuff like scrolling the screen and sprites are buttery smooth, just like in the original hardware.
- pozdnyshev 6y ago
  I would beg to differ. In fact, I would doubt many people could tell it apart in a blind test situation, especially on NES or SNES games. FPGA is just another expensive toy for hobbyists.

rtkwe 6y ago

There was a good article from Arstechnica a decade ago that pointed out why you need so much more power to get perfect emulation. To get exact emulation takes a lot of power because there are a few games which use odd tricks that are hard to document and precisely reimplement in software. FPGA emulation gets around that by more directly emulating the hardware. https://arstechnica.com/gaming/2011/08/accuracy-takes-power-one-mans-3ghz-quest-to-build-a-perfect-snes-emulator/ https://arstechnica.com/gaming/2011/08/accuracy-takes-power-...