11 ms·
Undocumented x86 instructions in Intel CPUs that can modify microcode
- mjg59 6y agoThe followup tweet indicates that the CPU has to be in an unlocked state before this is possible, which on a typical system requires there to be a Management Engine vulnerability first. Given what we currently know, this is going to be interesting for people interested in researching the behaviour and security of Intel CPUs and might well lead to discovery of security issues in future, but in itself I don't think this is dangerous. Edit to add: https://www.intel.com/content/dam/www/public/us/en/security-advisory/documents/the-intel-csme-dam-vulnerability-cve-2018-3659-and-cve-2018-3643-whitepaper.pdf https://www.intel.com/content/dam/www/public/us/en/security-... is a discussion of a previous Intel security issue which includes a description (on page 6) of the different unlock levels. This apparently requires that the CPU be in the Red unlock state, which (in the absence of ME vulnerabilities) should only be accessible by Intel.
- deleted 6y ago[deleted]
- xwolfi 6y agoSo you mean, if I am a state actor able to kidnap the child of an Intel high level employee... say I m Joe Biden, I can ask Intel to... remote unlock my CPU and read arbitrary memory block ? Or you mean Intel had to physically handle your CPU with a debug cable or whatever ? Cause I really dont feel it s okay that the only safety we have from a newly discovered exploit is that there needs to be another newly discovered exploit :D
- tedunangst 6y agoDon't use CPUs from companies that have employees that can be kidnapped.
- thayne 6y agoDon't use CPUs from companies that have employees.
- fctorial 6y agoDon't use CPUs from companies.
- sodality2 6y agoDon't use anything
- mightyoj 6y agoDon’t
- sgtnoodle 6y agoDon't be so paranoid. Just build your own CPU from discrete NAND gates like everyone else.
- tartoran 6y agoA pen and paper is everything you need.
- colejohnson66 6y agoBut what if it’s some of that fancy paper or a pen that records everything you write! Might need to manufacture your own pen and paper now...
- smlss_sftwr 6y agoHold up there you don't know if someone's been tampering with the trees, you'll have to grow your own forest first
- mjg59 6y agoRemotely? I think Intel would need to produce a backdoored ME firmware, get the system vendor to incorporate that into a system update and then convince the target to flash that. In that sense I don't know that they'd technically need physical access, but it doesn't really meet most people's description of a remote attack.
- scaramanga 6y agoIt is public knowledge that US intelligence agencies actually just hijack computers and equipment on their way to the customer and install hardware backdoors there (Snowden et al., 2014). It is also known that they have had backdoors in commercial systems as they came off the shelf, but I think usually those were CIA owned and controlled companies like the crypto AG phones. What is unknown (pure speculation) is whether, for example, Intel CPUs come backdoored straight from the factory floor? On the one hand, that would be a powerful capability to have, but on the other hand, the risk of exposure and subsequent damage to the US economy, prestige, etc. would be non-zero. So it's hard (for a plebian like me, anyway) to estimate how those costs/benefits might be weighed up by the US government.
- boomboomsubban 6y ago>What is unknown (pure speculation) is whether, for example, Intel CPUs come backdoored straight from the factory floor? There is also a third possibility, that some intelligence agency invested a ton of cash into finding abusable exploits in these systems giving them the same access a backdoor would provide. Also from the Snowden leaks, we know that they have programs with budgets in the millions into finding similar exploits and that there were similar programs outside Snowden's clearance. And though a bug may cause the same damage to the economy, it wouldn't hurt US prestige in the same way.
- jeffbee 6y agoBudgets in the millions, eh? So two full-time engineers?
- boomboomsubban 6y agoSorry, I misremembered the details. Around $400 million a year for the one program we have details on.
- rblatz 6y agoIf I'm the CIA I have dozens of highly placed agents or at least informants at Intel. Not necessarily placing backdoors, but finding and not fixing exploits and sending them back to the CIA for later use. It would be extremely cheap, hell if I'm China, Russia, the UK, or Israel I'm doing the same thing.
- strstr 6y agoThis seems like yet another thing on the list of “x86 hardware issues that sound worse than they are”. I’m interested to see what people are able to reverse engineer with these sorts of tools. It wasn’t even that long ago that ucode wasn’t even encrypted with integrity. I don’t think AMD started doing that until around 2010. I’m also curious which hardware versions this works on, since it’s not obvious it’s universal. I’ll be amused if it’s some forlorn low power chip from 10 years ago.
- gruez 6y ago>It wasn’t even that long ago that ucode wasn’t even encrypted with integrity whether they're encrypted or not doesn't really matter. what actually matters is whether they're signed or not. There was a talk given in 2017 about trying to modify the microcode in AMD processors, but they were using processors from a decade ago (AMD K10, introduced 2007). That makes me think that processors made in the past decade are probably using signed microcode.
- deleted 6y ago[deleted]
- colejohnson66 6y agoIs it this one? https://www.usenix.org/system/files/conference/usenixsecurity17/sec17-koppe.pdf https://www.usenix.org/system/files/conference/usenixsecurit...
- gruez 6y agoYeah, although I didn't find the original paper. Reading into it more, they mention when AMD and Intel started signing their microcode. >Note that Intel started to cryptographically sign microcode updates in 1995 [15] and AMD started to de-ploy strong cryptographic protection in 2011 [15].
- dooglius 6y agoThis would still break SGX/remote attestation, no? The chip can correctly say it's running some piece of assembly but if "ret" has been redefined to do whatever I want...
- userbinator 6y agoThat would be a good thing, given what those features are usually used for (DRM and other user-hostility).
- deleted 6y ago[deleted]
- sodality2 6y agoThis is what I'm interested in since they pushed that so heavily.
- strstr 6y agoThe keys are stripped out if you put it into the required unlock mode.
- tkinom 6y agoI would love ability to redefine call/ret to profile an app without compiler generate diff code.
- vlovich123 6y agoCan’t you do that through ebpf?
- tkinom 6y agoMy understand of ebpf can hook into the function calls in linux kernel. Can one do that on user space app?
- 6y ago
- runjake 6y agoPlot twist: there’s been a few ME vulnerabilities. And who knows what other purposeful ME backdoors there may or may not be.
- mjg59 6y agoSure, which is why this is useful to researchers. But the access someone needs to your system in order to exploit the ME vulnerabilities is sufficiently extreme that if someone achieves it you probably have other things to worry about.
- m3kw9 6y agoOr the only thing to worry about
- spacemanmatt 6y agoI can't get with justifying one serious security problem using another. Attackers increasingly combine local privilege escalations to move laterally, but only need one RCE to get in.
- mjg59 6y agoWindows can be booted into test keys mode, which allows the loading of unsigned drivers. We don't consider that a security issue because the privileges you need in order to switch to that mode are equivalent to the privileges you get by switching to that mode. It's the same here - the ME is the root of trust on Intel platforms. If you're in a position to execute arbitrary code on the ME then you've already got the ability to compromise the rest of the system enough to run arbitrary code on the host CPU, and being able to modify microarchitectural state doesn't give you additional privileges.
- vlovich123 6y agoI’m not saying that’s the case here, but that’s the general problem with the line of reasoning that “hey if you already have permission X then doing Y is the least of your concerns”. The concept of defense in depth literally relies on each barrier being independent and robust. That’s why you see hardening of Linux’s hibernate even though the common refrain is “well if you have physical access the game is lost”. There are things that even root can’t do even though “hey if you have root the game is lost”. The point of the game is to never lose even in very adverse environments.
- yjftsjthsd-h 6y agoNothing against the original post (which just says what they found), but this seems to be really overblown. Yes, of course Intel has instructions to update the micro code, since that's a thing that they do. Neither is it particularly surprising that they didn't bother to document operations that only they would ever have reason to use (in their eyes). If, as sibling comment notes, you have to be in a specific unlocked state to use this instruction, it should be perfectly safe assuming someone hasn't compromised other layers of security. So yes, this is certainly interesting, and it could be used as part of a chain of exploits to do some really nasty things, but by itself this seems like barely news?
- intricatedetail 6y agoShould products be fully documented so that consumers can make an informed decision?
- yjftsjthsd-h 6y agoI don't know. It's Windows vs Linux all over; I think Open is better, but Intel has never (AFAIK) pretended to do that. If a customer knows "Intel/Microsoft controls this", I personally feel like that's an acceptable tradeoff. And for people who find that unacceptable, there's Debian on POWER9. But if you're picking Intel, it's not like these opcodes change anything; we already have ME sitting there controlling the machine.
- intricatedetail 6y agoDid they release specs so that customer could build their own ME to manage the CPU? That would be interesting.
- google234123 6y agoWhy would they do that?
- 6y ago
- bedros 6y agoGood thing Apple is moving to M1; no more of that Intel crap. and stick with AMD for Linux.
- userbinator 6y agoI wonder what interesting things are in Apple's completely undocumented chips? There is that famous saying about known unknowns and unknown unknowns...
- olliej 6y agoNo more or less so than intel or amd. Or is the problem that the entire implementation is not public? Because even risc5 doesn't require that.
- mhh__ 6y agoThat isn't true. AMD aren't great at it, but Intel publish thousands and thousands of pages of manuals. They don't have the secret sauce in them as per se but Apple literally will not publish jack shit about anything inside M1.
- userbinator 6y ago"Intel x86 documentation has more pages than the 6502 has transistors": https://news.ycombinator.com/item?id=13126248 https://news.ycombinator.com/item?id=13126248 There's also the "unpublished" stuff that occasionally leaks here and there; not something which I suspect will ever happen with Apple, but you never know...
- wealthyyy 6y agoM1 Jackshit ahahhaha
- Daho0n 6y agoUntrue. There're more documentation on Intel's CPU than Apple provide on an entire M1 laptop.
- ExcavateGrandMa 6y agoOh my god we need change processor again? :Ð
- 29athrowaway 6y agoCan it be used to make RDRAND always return the same number?
- colejohnson66 6y agoNah. Just use an AMD Ryzen for that: https://almonde.org/posts/how-to-check-for-rdrand-bug-on-ryzen/ https://almonde.org/posts/how-to-check-for-rdrand-bug-on-ryz...
- tomrod 6y agoAs someone who isn't versed in computer hardware engineering, can nothing be done here? Why is it there is a new backdoor every few months? Is it an architecture issue, and we simply demand too much for too cheap? How do we lock this down?
- jeffbee 6y agoThis post is a nothing-burger. That an instruction exists that permits microcode updates is not new knowledge. Obviously there is one, if you can update microcode. All that's new here is reverse-engineering has filled in one of the holes in the Intel SDM.
- monocasa 6y agoThe previous publicly known mechanism required signed updates. This mechanism allows anyone to twiddle the bits.
- usr1106 6y ago> This mechanism allows anyone to twiddle the bits. This remained unclear to me. Other comments say the CPU needs to be in red unlocked state, whatever that is. The screenshot shows UEFI. So one could guess the CPU is in such state before the operating system gets loaded. But the operating system typically loads a microcode update, after that the CPU should no longer be in unlocked state. So for "everyone can fiddle with the bits", that would require to run a modified bootloader first. Which should not be possible thanks to secure boot. So yes, maybe it's a small step to another highly complex exploit. But it's not that everybody running a securely booted operating system (which should be everybody) can start fiddling with bits. Edit: There is a difference between your own bits and someone else's bits. Yes, on your own machine you can run a modified bootloader and that's a good thing. Putting a modified bootloader to another machine should not be possible (until someone breaks secure boot, but I don't think that has publicly happened)
- tinus_hn 6y ago
- moonchild 6y agoThe instruction in question looks to be encoded as 0f 0a. Which, sure enough, is missing from the official reference - https://files.catbox.moe/ktzqfg.png https://files.catbox.moe/ktzqfg.png
- userbinator 6y agoAccording to https://www.geoffchappell.com/notes/windows/archive/linkcpu.htm https://www.geoffchappell.com/notes/windows/archive/linkcpu.... this was at one point a proposed cache flush instruction (as the mnemonic suggests). More detailed information here: https://www.os2museum.com/wp/curious-instructions/ https://www.os2museum.com/wp/curious-instructions/
- _kbh_ 6y agothe other appears to 0f 0e. at least if you go off this tweet. https://twitter.com/eigma/status/1373155650432290819 https://twitter.com/eigma/status/1373155650432290819 . 0f 0e is a 3DNow! instruction that AMD supported but not intel, which would explain why it has a mnemonic in Ghidra even though its undocumented for Intel processors.
- moonchild 6y agoInteresting. Not sure how trustworthy that account is. The only 2-byte sequence documented by amd and not by intel that starts with 0f is, in fact, 0f 0e; that is FEMMS, which does match up with the length of the obscuring bar in the first reply. And it does seem plausible that intel would pick proximal instructions for 'read' and 'write' of uarch state.
- _kbh_ 6y agoOnly reason I consider it trust worthy is that it was retweeted by Mark Ermolov, which makes me think they got it right.
- BXLE_1-1-BitIs1 6y agoThe Chinese and other state actors may have already dug it up, or been provided it.
- deleted 6y ago[deleted]
- dreamcompiler 6y agoNow the question is "What does the microarchitecture really look like so we can write our own x86 microcode?"
- colejohnson66 6y agoThe problem with microcode is that it’s specifically tailored to each specific microarchitecture. The microcode for, say, Skylake, won’t work on Haswell. And it definitely won’t work on any AMD CPU. Intel and AMD almost certainly have compilers/assemblers of sorts that handles turning the microcode assembly-of-sorts into the correct bits, but they’re not portable.
- dreamcompiler 6y agoI'd settle for a single specific microarchitecture, just to see what was possible.
- colejohnson66 6y agoOh for sure. Even if it’s the P6’s microcode (the first with updatable code), I’d take it. I’ve always wondered what microcode looks like in these processors, and how it functions. There is “p6tools”[0][1] which looks interesting. But if Intel released info on it, that’d be really cool. Sidenote: Ken Shirriff has reverse engineered the ARM1’s microcode,[2] but it’s a “horizontal” microcode (bits control CPU blocks directly) while x86 uses “vertical” (RISC-like) microcode. [0]: https://github.com/peterbjornx/p6tools https://github.com/peterbjornx/p6tools [1]: https://www.youtube.com/watch?v=4oFOpDflJMA https://www.youtube.com/watch?v=4oFOpDflJMA (slides: https://hardwear.io/netherlands-2020/presentation/under-the-hood-of-a-CPU-hardwear-io-nl-2020.pdf https://hardwear.io/netherlands-2020/presentation/under-the-...) [2]: http://www.righto.com/2016/02/reverse-engineering-arm1-processors.html http://www.righto.com/2016/02/reverse-engineering-arm1-proce...
- Havoc 6y agoReminds me of GKH story about not even kernel devs truly understanding CPUs. Here is the timestamp https://youtu.be/t9MjGziRw-c?t=585 https://youtu.be/t9MjGziRw-c?t=585
- userbinator 6y agoLook up "Intel VISA" if you want to go down one of the many rabbitholes of undocumented x86... it makes me sad that there are whole subsystems in the hardware whose documentation is not publicly available; not from the security perspective, but from the "I bet someone could do some really interesting things with this functionality" perspective, like what LOADALL enabled (unreal mode, real-mode paging, etc.) decades ago. Intel isn't alone; search "9c5a203a" for some equally interesting stuff on the AMD side.
- peter_d_sherman 6y agoSure, I'll bite! <g> I've been down so many "rabbit holes" aka "levels of abstraction" aka "abstraction hierarchies" aka "turtles on top of turtles" aka "things stacked on top of other things" (compare with Monty Python's "society for putting things on top of other things") in my life as a Programmer (and in my secret life as an Philosopher! Shhh, don't tell anyone! <g>. And yes, I know... "Keep the day job"...<g>) that one more ("I'll go down this last rabbit hole, and then I'll be finished, really!") really won't make that much more difference! <g> Before I get started on that one though, two more quick references about "abstraction hierarchies" aka "rabbit holes". On the one hand, we have Joel Spolsky's magnificent essay, "The Law of Leaky Abstractions (https://www.joelonsoftware.com/2002/11/11/the-law-of-leaky-abstractions/ https://www.joelonsoftware.com/2002/11/11/the-law-of-leaky-a...) and on the other, we have the Biblical story of "The Tower Of Babel". Now, I am not the member of any religion, I don't endorse any religious text over any other, but any intellectual worth his salt -- should read both of these writings, and compare them. Once you've done that, then compare what's being said to abstraction hierarchies of all sorts. We see abstraction hierarchies in code, we see them in language (especially when a language changes over many years, as it changes, fractures and sediments). We see them in Law (Law in the U.S. as it is practiced today can be compared to an abstraction hierarchy -- not at all unlike The Tower Of Babel as a metaphor for this phenomenon, or Joel's essay as a more complete modern-day explanation of it...) We see them in a number of places and systems. We even see them in x86-land... That's because the x86 (as far as all of my research has suggested, and someone correct me if you think I am wrong, with links/references please!) -- is really a RISC core with a separate microcode execution engine (the level of abstraction above the RISC core), and has been since at least the Pentium Pro (P6, 1995): https://stackoverflow.com/questions/5806589/why-does-intel-hide-internal-risc-core-in-their-processors https://stackoverflow.com/questions/5806589/why-does-intel-h... http://i.blackhat.com/us-18/Thu-August-9/us-18-Domas-God-Mode-Unlocked-Hardware-Backdoors-In-x86-CPUs.pdf http://i.blackhat.com/us-18/Thu-August-9/us-18-Domas-God-Mod... (Or Google "Christopher Domas God Mode Unlocked") (Also, see the patents listed in this PDF) https://arxiv.org/pdf/1910.00948v1.pdf https://arxiv.org/pdf/1910.00948v1.pdf https://troopers.de/events/troopers16/655_the_chimaera_processor/ https://troopers.de/events/troopers16/655_the_chimaera_proce... ("We take a 12-core processor, inject microcode to simulate a PowerPC (2 cores) and a MIPS processor (2 cores), restrict 2 cores to i386 and leave 4 cores to amd64.") So with all this in mind, let's turn back and look at VISA: https://threatpost.com/undocumented-intel-visa-tech-can-be-abused-researchers-allege/143283/ https://threatpost.com/undocumented-intel-visa-tech-can-be-a... >"The Intel technology is called Visualization of Internal Signals Architecture (VISA), and is used for manufacturing-line testing of chips. However, Maxim Goryachy and Mark Ermolov, security researchers with Positive Technologies, said in a Thursday Black Hat Asia session that VISA can be accessed – and subsequently abused — to capture data from the CPU using a series of previously-disclosed vulnerabilities in Intel technology." You know, that sort of reminds me of lyrics from The Who's "You Better You Bet": "I showed up late one night with a neon light for a VISA, But knowing I'm so eager to fight can't make letting me in any easier..." Hmmm, now who is "me" in the above context? ? Could it be... (With my apologies to SNL's Dana Carvey as "The Church Lady")... a TLA? (Three Letter... er, group? <g>) Hey, if any power-that-be is offended, then I'd like them to know that I only quote things that I find on some places on the Internet -- on other places on the Internet.... In other words, I am only the messenger... one of millions and billions, that also quote things that they find on the Internet -- on other places on the Internet... (Side note: There should be a Monty Python sketch for that topic! <g>) In other words, "don't shoot the messenger...(s)" <g>...
- LockAndLol 6y agoSo, which CPUs are actually open-hardware and available to consumers with mainboards that support them? Is RISC-V going to be this?
- floatboth 6y agoNone. Well, yeah, I think SiFive has HDL sources for quite a lot of their stuff up on GitHub, but it's not like you can just compile them into production silicon at home, heck, you can't even verify that the silicon was actually compiled from that source. (Yes there's research into verifiable silicon, but it's not like everyone has ultra high end electron microscopes and whatnot at home lol) And of course nothing about RISC-V implies that production implementations will be open source at all.
- lurtbancaster 6y agoIs there a way to use this for consumer good? 1. Like unofficially turning on ECC support on non-ECC chips assuming the hardware allows for it? 2. Or increasing total supported RAM size on lower end chips? 3. Unofficial open-source microcode updates(performance/security) for older unsupported chips?
- BlackLotus89 6y agoThere was an interesting black hat talk about automatically finding undocumented instructions. [0] Interesting comment on twitter to the instruction of the original post[1] [0] https://www.youtube.com/watch?v=KrksBdWcZgQ&t=3 https://www.youtube.com/watch?v=KrksBdWcZgQ&t=3 [1] https://twitter.com/eigma/status/1373155650432290819 https://twitter.com/eigma/status/1373155650432290819