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170 GHz is the speed of a PLL published by a popular chip designer on youtube a decade ago in 130nM SiGe BiCMOS. The "100GHz" headline tempts comparison to CPU
by jjoonathan 6y ago
170 GHz is the speed of a PLL published by a popular chip designer on youtube a decade ago in 130nM SiGe BiCMOS.
The "100GHz" headline tempts comparison to CPU clock speeds but those are absolutely not the right point of comparison. GHz doing one thing != GHz doing another. CPU clock cycles are very deep compared to a bit-serial adders and operate under heavy thermal constraints. To compare apples to apples, we need to know: what is the speed of a bit-serial adder in near-future CMOS? Silicon bipolar? 3-5 bipolar?
My guess: you could implement a 100GHz bit serial adder in CMOS today and get several hundred GHz if you dropped thermal constraints, went bipolar, etc. That doesn't invalidate the research -- we need more public cutting-edge device research, not less -- but the posts assuming this result translates to 100GHz CPUs are getting a bit ahead of themselves.
- mlyle 6y agoAs you say-- it depends upon what you're doing. Comparing a PLL to an adder is silly. > My guess: you could implement a 100GHz bit serial adder in CMOS today 7nm FINFET CMOS will get you to roughly the same performance point. It's also quite mature compared to the technique in the article.
- jjoonathan 6y ago> Comparing a PLL to an adder is silly. Yeah, but comparing a bit adder to a 64 bit full adder integrated into a modern CPU clock cycle is really silly :) Glad to hear my intuition about modern CMOS was in the ballpark though. I've been out of this scene for the better part of a decade.
- mlyle 6y agoRing oscillators and bit adders and 30 gate benchmark circuits are how we characterize processes. We don't try and fabricate a superscalar CPU on our first round trips through developing a new process let alone new transistor types. This is doing quite well for early rounds on this technique.
- jjoonathan 6y agoAre any of those figures public? I did a cursory search but couldn't find them so I went with slightly silly clickbait on the rationale that it was an order of magnitude less silly than the other comparisons being made in the thread. I stand by that: as "benchmarks," a bit adder is much closer to a PLL divider than a 64 bit full adder in a CPU cycle. I fully agree that there's another order of magnitude before the comparison starts to become apples-to-apples, or bit-adders to bit-adders, but you're going to have to help with the search if you want to see it happen.
- mlyle 6y agoWhat figures, exactly? Here, we're discussing a paper characterizing the current version of the process first with ring oscillators and measured delays through a single cell, and then with a serial bit adder, so.. if you mean those, yes?
- jjoonathan 6y agoI mean can you find the bit adder figures for, say, TSMC N7 or N5? I poked around google scholar and wikipedia for a few minutes before giving up and hoping that someone up with the times would know exactly where to look.
- mlyle 6y agoNo. Those are subject to NDA, but are broadly similar in fmax and prop time under reasonable voltages. I think it's exciting here that they're dicking around with new technologies in their infancy, and in a few coarse design changes of cells went from 60% of CMOS leading edge to about the same numbers. Of course, total system power, etc, is atrocious, considering that this is cryogenic, etc. You need a lot of logic before this could come ahead in efficiency.
- jjoonathan 6y ago> No. Those are subject to NDA Yeah, that's what I thought and why I settled for a less accurate comparison. > I think it's exciting I think it's exciting, too. The extent of my claims is "no, this does not mean 100GHz LN2 CPUs in a few years." I did not intend these remarks to be meaningful to chip designers, only to CPU consumers who see "GHz" and think "CPU clock speeds." The leverage of having a slightly better fundamental device is extraordinary. We should spare no expense looking for them and leave no stone unturned.
- jandrese 6y agoSignal propagation time seems like it should be an issue at 100Ghz. Light only travels about 3mm per clock cycle at that speed. A circuit built at that speed will need absurdly deep pipelines to do much more than single bit adding.