5 ms·

Interestingly, the M1 (and probably other Apple Silicon CPUs) is an exception: % sysctl hw.cachelinesize hw.cachelinesize: 128

zeusk 6y ago
That's an ARM thing afaik, the snapdragons I work with also use 128 byte cacheline.
- 38491239821398 6y ago
  A quick search suggests ARM's own designs tend to use 64-byte cache lines, but perhaps this is something the SoC vendors can customize? AFAIK, Qualcomm's recent parts use ARM-designed cores.
  - zeusk 6y ago
    Actually you're right, recent designs use 64 byte because of things like this https://www.mono-project.com/news/2016/09/12/arm64-icache/ https://www.mono-project.com/news/2016/09/12/arm64-icache/ Perhaps, either Apple is fooling the userspace software or is using 128b cachelines for their little cores too.
    - 38491239821398 6y ago
      It looks like sysctl shows the cache info for the little cores, at least by default: hw.cachelinesize: 128 hw.l1icachesize: 131072 hw.l1dcachesize: 65536 The reported L1I and L1D matches up with the little cores. Also very interesting: if you run sysctl under Rosetta, it reports 64 bytes: % arch -x86_64 /bin/bash -c "sysctl hw.cachelinesize" hw.cachelinesize: 64 This information is exposed specifically so that app developers can optimize for the cache line size in use. I very much doubt Apple would report a false number. As for Samsung: my guess is that Apple has been using 128-byte cache lines for a long time, and Samsung simply copied that because Apple did it, without understanding the implications. That would be totally in line with what I expect from them.
      - zeusk 6y ago
        > This information is exposed specifically so that app developers can optimize for the cache line size in use. I very much doubt Apple would report a false number. No, this number is used for compatibility reasons. OS is free to pull shenanigan behind apps to take care of CPU cache line size changing underneath them (like using a larger size so it'll align on everything; 128b aligned is 64b aligned too).

zeusk 6y ago

That's an ARM thing afaik, the snapdragons I work with also use 128 byte cacheline.

38491239821398 6y ago
A quick search suggests ARM's own designs tend to use 64-byte cache lines, but perhaps this is something the SoC vendors can customize? AFAIK, Qualcomm's recent parts use ARM-designed cores.
- zeusk 6y ago
  Actually you're right, recent designs use 64 byte because of things like this https://www.mono-project.com/news/2016/09/12/arm64-icache/ https://www.mono-project.com/news/2016/09/12/arm64-icache/ Perhaps, either Apple is fooling the userspace software or is using 128b cachelines for their little cores too.
  - 38491239821398 6y ago
    It looks like sysctl shows the cache info for the little cores, at least by default: hw.cachelinesize: 128 hw.l1icachesize: 131072 hw.l1dcachesize: 65536 The reported L1I and L1D matches up with the little cores. Also very interesting: if you run sysctl under Rosetta, it reports 64 bytes: % arch -x86_64 /bin/bash -c "sysctl hw.cachelinesize" hw.cachelinesize: 64 This information is exposed specifically so that app developers can optimize for the cache line size in use. I very much doubt Apple would report a false number. As for Samsung: my guess is that Apple has been using 128-byte cache lines for a long time, and Samsung simply copied that because Apple did it, without understanding the implications. That would be totally in line with what I expect from them.
    - zeusk 6y ago
      > This information is exposed specifically so that app developers can optimize for the cache line size in use. I very much doubt Apple would report a false number. No, this number is used for compatibility reasons. OS is free to pull shenanigan behind apps to take care of CPU cache line size changing underneath them (like using a larger size so it'll align on everything; 128b aligned is 64b aligned too).