5 ms·

Everything old is new again. They tried this with FB-DIMMs in the early 2000s and it didn't go well: https://en.wikipedia.org/wiki/Fully_Buffered_DIMM https:/

Everything old is new again. They tried this with FB-DIMMs in the early 2000s and it didn't go well: https://en.wikipedia.org/wiki/Fully_Buffered_DIMM https://en.wikipedia.org/wiki/Fully_Buffered_DIMM That SERDES chip unavoidably increases latency, roughly doubling it. This isn't likely to catch on as the only kind of DRAM in the system; latency is too important. Maybe we'll see successful systems with two levels of DRAM: small low-latency parallel DRAM and a large heap of higher-latency serial DRAMs. That's plausible.

sitkack 6y ago
Main memory will move to an HBM, "regular" ram beyond the first 32,64 ... GB will be DDRX, then it will be pmem (Optane, etc). We will just keep getting more layers in the hierarchy.
- wahern 6y ago
  Yep. Because memory access fundamentally scales in O(sqrt(N)) time, not O(1). http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html
PhantomGremlin 6y ago
latency is too important Yeah, you would think so. But it really hasn't improved all that much over the years. (Of course, that's partially because it's hard to do!). Roughly speaking, when I designed with DRAM in 1983, the access time from RAS was 150 ns for the most popular parts. Now, with DDR4, you're talking CAS latency of about 10 ns, an improvement of 15x. In the same timeframe CPU clock rate increased from about 10 MHz to about 3000 MHz, an improvement of 300x. I grok your comment about perhaps having two levels of DRAM, but the whole memory hierarchy thing is already crazy. Most computers already have 3 levels of cache ahead of the DRAM.
- justaguy88 6y ago
  Latency is very important, but cost is even more important. If there was cheaper lower latency DRAM they'd use it
- datameta 6y ago
  With Storage Class Memory aka Persistent memory becoming a talked about thing in the industry they're not too far off base. It sits right between capacitive memory and nand flash; may end up being the DRAM's page file and the SSD's cache.
ardy42 6y ago
> Everything old is new again. They tried this with FB-DIMMs in the early 2000s and it didn't go well: IIRC, Rambus RDRAM was also serial, or at least less parallel than conventional DRAM.

sitkack 6y ago

Main memory will move to an HBM, "regular" ram beyond the first 32,64 ... GB will be DDRX, then it will be pmem (Optane, etc). We will just keep getting more layers in the hierarchy.

wahern 6y ago
Yep. Because memory access fundamentally scales in O(sqrt(N)) time, not O(1). http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html http://www.ilikebigbits.com/2014_04_21_myth_of_ram_1.html

PhantomGremlin 6y ago

latency is too important Yeah, you would think so. But it really hasn't improved all that much over the years. (Of course, that's partially because it's hard to do!). Roughly speaking, when I designed with DRAM in 1983, the access time from RAS was 150 ns for the most popular parts. Now, with DDR4, you're talking CAS latency of about 10 ns, an improvement of 15x. In the same timeframe CPU clock rate increased from about 10 MHz to about 3000 MHz, an improvement of 300x. I grok your comment about perhaps having two levels of DRAM, but the whole memory hierarchy thing is already crazy. Most computers already have 3 levels of cache ahead of the DRAM.

justaguy88 6y ago
Latency is very important, but cost is even more important. If there was cheaper lower latency DRAM they'd use it
datameta 6y ago
With Storage Class Memory aka Persistent memory becoming a talked about thing in the industry they're not too far off base. It sits right between capacitive memory and nand flash; may end up being the DRAM's page file and the SSD's cache.

ardy42 6y ago

> Everything old is new again. They tried this with FB-DIMMs in the early 2000s and it didn't go well: IIRC, Rambus RDRAM was also serial, or at least less parallel than conventional DRAM.