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What’s your opinion about SystemVerilog? Can it be used as a higher level language compared to VHDL? Or it is still on same level?

• WillFlux 6y ago
  SystemVerilog has several useful additions for FPGA engineers, but tool support has been slow to materialise. For the moment, I’ve kept to the few features that Xilinx Vivado and Yosys http://www.clifford.at/yosys/ http://www.clifford.at/yosys/ are both happy with, such as enums, logic data type, and always_ff etc. I’ve not used VHDL in anger, so can’t give you a useful opinion there.
• sguav 6y ago
  Doing VHDL designs for a living here, using SystemVerilog once in a while when absolutely required. Take my words with a good pinch of salt! SV is anyway a hardware description language, so you still think and code in terms of modules and signals (wires) to be connected. But if you want to create structures that use variables and have a more "procedural" style, I find that SV is more agile than VHDL for this specific purpose. If you want real high level languages for hardware there are tools that provide synthesis from C/C++, Python and more software oriented languages.
  • rbanffy 6y ago
    > there are tools that provide synthesis from C/C++, Python and more software oriented languages That sounds extremely interesting!
    • imstate 6y ago
      Beware, its much harder to get the correct hardware design useing these tools. If that doesn't matter, then go for it!
      • rbanffy 6y ago
        I would imagine that. A functional language like Haskell would probably be easier to compile to hardware.