46 ms·

What is the benefit of smaller transistors? Serious question. Why does it matter if I have 7nm vs. 5nm vs. anything else?

tryptophan 6y ago
Smaller distance -> lower resistance -> less heat -> higher clocks/more stuff per clock allowed with same amount of heat produced -> higher performance.
- algorithm314 6y ago
  No smaller dimensions -> thinner wires -> higher resistance per length.
  - marcosdumay 6y ago
    A chip is not composed of cylindrical wires. Smaller dimensions means you can set a smaller length for the wire. As you can see on the diagram on this article, there is a large push into increasing the height of the transistors. That has being going on for more than a decade. About the width, a finer process means you can keep the width of the most critical transistors the same, but can also trade it off into less width (and performance) where it is less important. So, overall, smaller dimensions leads to lower resistances. You can trade some of the gain for density, but you'll always get some lower resistance.
- systemvoltage 6y ago
  None of these reasons are as important as transistor count / mm^2. If you can shrink die size in half, you can effectively reduce its cost by half as well. Processing wafers through 400 steps in the fab and its capacity is limited by how many useful chips you can build on a given 300mm wafer.
- baybal2 6y ago
  > Smaller distance -> lower resistance -> less heat -> higher clocks Smaller distance -> lower capacitance -> higher clocks
deleted 6y ago
[deleted]
LatteLazy 6y ago
Smaller means closer together. Closer together means less time for a signal to move from one to another. Less time means higher clock speeds. If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.
- coolspot 6y ago
  > If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz. 100mm across is 10cm, 0.1m, 4 inches. That’s palm-sized CPU - far from any modern silicon.
  - LatteLazy 6y ago
    The reason we have shrunk the CPU is because the transistors etc that used to take 100mm can now be held in 10mm. Theres always this trade off between complexity and speed. Making the components smaller means you can have both!
  - deleted 6y ago
    [deleted]
- cactus2093 6y ago
  I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller and closer together. Seems like an intriguing napkin math limit/simplification though, I'd be interested if anyone could elaborate on if there's any substance to it.
  - corty 6y ago
    It is not wrong, it is rather correct. Speed of propagation in semiconductor materials is at most a third of speed of light in vacuum. So the distance travelled is rather limited for a signal. Also, a signal might have to traverse a few transistors or gates, so frequency in the 3GHz range does really limit processor sizes to the order of millimeters. You already said how to get around it: Pipelines, that limits the area a signal has to propagate. Also, one has to take care to make signals arrive early enough in the longest possible signal path as well as to distribute the clock in a way for it to arrive at aligned times everywhere, so you need a clock distribution net with known delays, etc. Chip timing is black art.
lizknope 6y ago
Smaller distance to travel so signals get from one gate to another quicker which will enable a higher clock speed. Smaller devices use less power so less heat and longer battery life. Smaller devices mean a smaller chip which is cheaper (although mask costs will be more expensive) or use the extra area for more features like more cache or another processor core.
jabl 6y ago
The marginal cost of manufacturing a chip is roughly proportional to area. So with smaller transistors you can fit more of them into a given area.
- superrad 6y ago
  Exactly, the smaller your chip is the more you can fit on a silicon wafer. If your chip is too large it can even make it practically impossible to manufacture at scale due to the increased chance of defects as your chip size increases.
t-writescode 6y ago
It's crazy to think about if you've never thought about this, but the speed of light is a bottleneck for processors. When we get smaller devices, there's literally less distance that needs to be traversed, so more can be done!
- adwn 6y ago
  > the speed of light is a bottleneck for processors It's not the speed of light [in a vacuum], but electric signal propagation speed in copper.
  - SpaceRaccoon 6y ago
    And the "electric signal" is an electromagnetic wave- also known as light. Nowhere did they imply the speed of light in a vacuum, the speed of light in copper is an equally valid interpretation.
    - mhh__ 6y ago
      That's true but it's easy to forget that the velocity factor of that wave is significantly smaller in (say) copper than air or a vacuum.
      - SpaceRaccoon 6y ago
        The velocity factor of light in glass is also significantly smaller, about 70%.
    - adwn 6y ago
      > And the "electric signal" is an electromagnetic wave- also known as light. No, it's not. If it were, you'd have photons moving through your copper wire, which would be quite the sensation! A moving electron does create a change in the electromagnetic field, however, so maybe that's where your confusion stems from?
      - ben_w 6y ago
bigmattystyles 6y ago
You can pack more within the same area for one. A multitude of other constraints come in but that’s a big reason.
ksec 6y ago
> Serious question... To Oversimplify. With a Fixed Yield, and an exact 100% increase in Transistor Density that translate to 50% smaller Die Size. On a Wafer, that would equate to Double the amount Die you have. All of a sudden your profits increase dramatically. 5nm also have a better power curve so within the same clock speed you have lower energy usage. Hence you can push for higher performance if needed. The first point of Uni Economics is important for the industry. If you have high enough volume, say hundreds Million of chips per year then it make sense to move to the next node for cost saving. If you have small volume or low margin chip then the Design Cost, which is the most expensive part of chip making, would not work to your benefits. And it also depends on Wafer price, If 5nm is Double the Price of 7nm then in the above example your unit cost would be exactly the same. The second point is important for CPUs, and other things that are increasingly computational expensive like WiFi 6 and 5G Modem. You want your Smartphone to last longer on battery so they work better on an energy efficient node. So basically it is a Cost / Performance trade offs.
femto113 6y ago
The numbers roughly correspond to the width of wires in the circuits, but the number of circuits you can fit per unit area depends on the square of that number so going from 7nm to 5nm roughly doubles density. The first microprocessor[1] was around 10,000nm so we're approaching 5,000x thinner wires or almost 25 million times more circuits (the latest Apple M1[2] is at 5nm have about 8,000,000x as many transistors as the 4004). [1] https://www.intel.com/content/www/us/en/history/museum-story-of-intel-4004.html https://www.intel.com/content/www/us/en/history/museum-story... [2] https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/ https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/
mng2 6y ago
Besides being able to pack more transistors into a given area, a smaller transistor has less gate capacitance (to first order). This means it can switch faster (smaller RC time constant) and less energy is expended in switching. Thus, going from generation to generation, the overall energy expenditure of a chip can be kept within a reasonable range despite adding many more transistors. You also may have heard of a "die shrink", where an existing design gets shrunk to the next technology node, using less power and clocking faster. Shrinking isn't always a walk in the park though. Some nodes ago subthreshold leakage became a big problem until they figured out how to solve it.

tryptophan 6y ago

Smaller distance -> lower resistance -> less heat -> higher clocks/more stuff per clock allowed with same amount of heat produced -> higher performance.

algorithm314 6y ago
No smaller dimensions -> thinner wires -> higher resistance per length.
- marcosdumay 6y ago
  A chip is not composed of cylindrical wires. Smaller dimensions means you can set a smaller length for the wire. As you can see on the diagram on this article, there is a large push into increasing the height of the transistors. That has being going on for more than a decade. About the width, a finer process means you can keep the width of the most critical transistors the same, but can also trade it off into less width (and performance) where it is less important. So, overall, smaller dimensions leads to lower resistances. You can trade some of the gain for density, but you'll always get some lower resistance.
systemvoltage 6y ago
None of these reasons are as important as transistor count / mm^2. If you can shrink die size in half, you can effectively reduce its cost by half as well. Processing wafers through 400 steps in the fab and its capacity is limited by how many useful chips you can build on a given 300mm wafer.
baybal2 6y ago
> Smaller distance -> lower resistance -> less heat -> higher clocks Smaller distance -> lower capacitance -> higher clocks

deleted 6y ago

[deleted]

LatteLazy 6y ago

Smaller means closer together. Closer together means less time for a signal to move from one to another. Less time means higher clock speeds. If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.

coolspot 6y ago
> If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz. 100mm across is 10cm, 0.1m, 4 inches. That’s palm-sized CPU - far from any modern silicon.
- LatteLazy 6y ago
  The reason we have shrunk the CPU is because the transistors etc that used to take 100mm can now be held in 10mm. Theres always this trade off between complexity and speed. Making the components smaller means you can have both!
- deleted 6y ago
  [deleted]
cactus2093 6y ago
I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller and closer together. Seems like an intriguing napkin math limit/simplification though, I'd be interested if anyone could elaborate on if there's any substance to it.
- corty 6y ago
  It is not wrong, it is rather correct. Speed of propagation in semiconductor materials is at most a third of speed of light in vacuum. So the distance travelled is rather limited for a signal. Also, a signal might have to traverse a few transistors or gates, so frequency in the 3GHz range does really limit processor sizes to the order of millimeters. You already said how to get around it: Pipelines, that limits the area a signal has to propagate. Also, one has to take care to make signals arrive early enough in the longest possible signal path as well as to distribute the clock in a way for it to arrive at aligned times everywhere, so you need a clock distribution net with known delays, etc. Chip timing is black art.

lizknope 6y ago

Smaller distance to travel so signals get from one gate to another quicker which will enable a higher clock speed. Smaller devices use less power so less heat and longer battery life. Smaller devices mean a smaller chip which is cheaper (although mask costs will be more expensive) or use the extra area for more features like more cache or another processor core.

jabl 6y ago

The marginal cost of manufacturing a chip is roughly proportional to area. So with smaller transistors you can fit more of them into a given area.

superrad 6y ago
Exactly, the smaller your chip is the more you can fit on a silicon wafer. If your chip is too large it can even make it practically impossible to manufacture at scale due to the increased chance of defects as your chip size increases.

t-writescode 6y ago

It's crazy to think about if you've never thought about this, but the speed of light is a bottleneck for processors. When we get smaller devices, there's literally less distance that needs to be traversed, so more can be done!

adwn 6y ago
> the speed of light is a bottleneck for processors It's not the speed of light [in a vacuum], but electric signal propagation speed in copper.
- SpaceRaccoon 6y ago
  And the "electric signal" is an electromagnetic wave- also known as light. Nowhere did they imply the speed of light in a vacuum, the speed of light in copper is an equally valid interpretation.
  - mhh__ 6y ago
    That's true but it's easy to forget that the velocity factor of that wave is significantly smaller in (say) copper than air or a vacuum.
    - SpaceRaccoon 6y ago
      The velocity factor of light in glass is also significantly smaller, about 70%.
  - adwn 6y ago
    > And the "electric signal" is an electromagnetic wave- also known as light. No, it's not. If it were, you'd have photons moving through your copper wire, which would be quite the sensation! A moving electron does create a change in the electromagnetic field, however, so maybe that's where your confusion stems from?
    - ben_w 6y ago

bigmattystyles 6y ago

You can pack more within the same area for one. A multitude of other constraints come in but that’s a big reason.

ksec 6y ago

> Serious question... To Oversimplify. With a Fixed Yield, and an exact 100% increase in Transistor Density that translate to 50% smaller Die Size. On a Wafer, that would equate to Double the amount Die you have. All of a sudden your profits increase dramatically. 5nm also have a better power curve so within the same clock speed you have lower energy usage. Hence you can push for higher performance if needed. The first point of Uni Economics is important for the industry. If you have high enough volume, say hundreds Million of chips per year then it make sense to move to the next node for cost saving. If you have small volume or low margin chip then the Design Cost, which is the most expensive part of chip making, would not work to your benefits. And it also depends on Wafer price, If 5nm is Double the Price of 7nm then in the above example your unit cost would be exactly the same. The second point is important for CPUs, and other things that are increasingly computational expensive like WiFi 6 and 5G Modem. You want your Smartphone to last longer on battery so they work better on an energy efficient node. So basically it is a Cost / Performance trade offs.

femto113 6y ago

The numbers roughly correspond to the width of wires in the circuits, but the number of circuits you can fit per unit area depends on the square of that number so going from 7nm to 5nm roughly doubles density. The first microprocessor[1] was around 10,000nm so we're approaching 5,000x thinner wires or almost 25 million times more circuits (the latest Apple M1[2] is at 5nm have about 8,000,000x as many transistors as the 4004). [1] https://www.intel.com/content/www/us/en/history/museum-story-of-intel-4004.html https://www.intel.com/content/www/us/en/history/museum-story... [2] https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/ https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/

mng2 6y ago

Besides being able to pack more transistors into a given area, a smaller transistor has less gate capacitance (to first order). This means it can switch faster (smaller RC time constant) and less energy is expended in switching. Thus, going from generation to generation, the overall energy expenditure of a chip can be kept within a reasonable range despite adding many more transistors. You also may have heard of a "die shrink", where an existing design gets shrunk to the next technology node, using less power and clocking faster. Shrinking isn't always a walk in the park though. Some nodes ago subthreshold leakage became a big problem until they figured out how to solve it.