4 ms·

Interestingly, there is one dimension that still tracks the node number fairly closely. In fact, the node number has never referred to transistor dimension, bu

by nyunai 6y ago

Interestingly, there is one dimension that still tracks the node number fairly closely. In fact, the node number has never referred to transistor dimension, but the length of the gate electrode. A transistor would typically be about 4 times larger than that. The reason to refer to the length of the gate electrode is because that was always the smallest feature printed on the chip. And that is what defined the required resolution of the lithography process. So, a lithography process with a resolution of 32nm would be able to print chips with 32nm gate lengths. Much has changed, and now transistors are no longer planar, they are 3-dimensional fin structures (FinFETs). The gate length scaling has slowed down, and now is not the smallest feature on the chip anymore. The smallest feature in a modern FinFET process is actually the with of those 'fi s' that form the transistor channels. And as if by magic, they correspond pretty well to the node names, i.e. a 5nm process will have a fin width of about 5nm. You will likely not find that mentioned anywhere, it's just a fun fact that I noticed as a VLSI technologist.

kayson 6y ago
It's still a little disingenuous because most performance parameters are directly related to transistor lengths, whether finfet or not. There used to be a concept of "scaling" where you could roughly estimate that going from a 40nm process to a 28nm process, for example, would save you (28/40)^2 percent power. Finfet disrupted that to some extent, but it partly held true as physical lengths actually continued to decrease with node names. By now, though, it is generally understood that state-of-the-art process node numbers doesn't mean much in that regard. I also just checked a handful of processes I have access to, and at least in these cases, the fin width doesn't scale with the technology name (e.g. 5nm and 7nm has 8nm fin width drawn in layout, and model indicates 27nm "width" per fin). This isn't much of a surprise to me, because foundries are just decreasing the number with newer generations of the tech, even if the lithography (the method by which features are etched into the silicon) hasn't significantly changed. For example, 3 generations of a single process were called 7***, then 5***, then 4***.
- dnautics 6y ago
  > It's still a little disingenuous because most performance parameters That's your bias. To a process engineer the parameter that matters is what wavelength you are blasting the mask with and what size a feature it can create.
  - lumost 6y ago
    This is probably similar to the debate between management and engineers at Intel. As an outside observer who has never been near CPU design let alone process engineering - TSMC's nomenclature smacks of moving the goal post to claim a win. Despite the reality that from a process engineering standpoint decoupling the "transistor size" from the production node is an improvement and allowed TSMC to ship a technically superior process.
  - Guthur 6y ago
    And also does it actually matter. It ultimately refers to some improved denser semiconductor process which is what the customer is buying. These processes are not exactly standardised either it would be a major undertaking to take an architecture from TSMC 7nm to 5nm let alone moving from TSMC to Samsung, Global Foundaries or if at all possible Intel.
hinkley 6y ago
So essentially the 'node' size is the lithography process, not the chips you design with that process. You can't make a feature smaller than the lithography process, nor x.5 times as big as the resolution of the lithography. There will then be a bunch of parts of the chip that are just a little bigger or a little farther apart than they need to be. Not unlike how there are pipeline phases that are just a little longer than they theoretically could be (because all of their neighbors have to line up with each other). If you can fix the bottleneck then everything else can shine, causing a magical, outsized improvement.

by nyunai 6y ago

kayson 6y ago

It's still a little disingenuous because most performance parameters are directly related to transistor lengths, whether finfet or not. There used to be a concept of "scaling" where you could roughly estimate that going from a 40nm process to a 28nm process, for example, would save you (28/40)^2 percent power. Finfet disrupted that to some extent, but it partly held true as physical lengths actually continued to decrease with node names. By now, though, it is generally understood that state-of-the-art process node numbers doesn't mean much in that regard. I also just checked a handful of processes I have access to, and at least in these cases, the fin width doesn't scale with the technology name (e.g. 5nm and 7nm has 8nm fin width drawn in layout, and model indicates 27nm "width" per fin). This isn't much of a surprise to me, because foundries are just decreasing the number with newer generations of the tech, even if the lithography (the method by which features are etched into the silicon) hasn't significantly changed. For example, 3 generations of a single process were called 7***, then 5***, then 4***.

dnautics 6y ago
> It's still a little disingenuous because most performance parameters That's your bias. To a process engineer the parameter that matters is what wavelength you are blasting the mask with and what size a feature it can create.
- lumost 6y ago
  This is probably similar to the debate between management and engineers at Intel. As an outside observer who has never been near CPU design let alone process engineering - TSMC's nomenclature smacks of moving the goal post to claim a win. Despite the reality that from a process engineering standpoint decoupling the "transistor size" from the production node is an improvement and allowed TSMC to ship a technically superior process.
- Guthur 6y ago
  And also does it actually matter. It ultimately refers to some improved denser semiconductor process which is what the customer is buying. These processes are not exactly standardised either it would be a major undertaking to take an architecture from TSMC 7nm to 5nm let alone moving from TSMC to Samsung, Global Foundaries or if at all possible Intel.

hinkley 6y ago

So essentially the 'node' size is the lithography process, not the chips you design with that process. You can't make a feature smaller than the lithography process, nor x.5 times as big as the resolution of the lithography. There will then be a bunch of parts of the chip that are just a little bigger or a little farther apart than they need to be. Not unlike how there are pipeline phases that are just a little longer than they theoretically could be (because all of their neighbors have to line up with each other). If you can fix the bottleneck then everything else can shine, causing a magical, outsized improvement.