6 ms·

Can someone explain the technical benefits of this architecture over the competition? That is should I be excited if I don't care about e.g. openness? Or is it

Can someone explain the technical benefits of this architecture over the competition? That is should I be excited if I don't care about e.g. openness? Or is it simply an effort to create something that is a half-decent cpu alternative but open? Is there anything about RISC-V that is "better" simply because it is a later design than others? Is it likely to evolve faster because it is open or more modern?

tyingq 6y ago
I think in the real world "No percentage of each sale payments to ARM" is what will drive RISC-V. An "open" ISA doesn't force anything else to be open. So, use cases like Western Digital, where they can quit paying ARM a percentage of every hard drive they sell, for example. As for technical advantages, each RISCV vendor has their own choice of how to implement, so it's hard to say anything broad that applies to all RISCV implementations. The Berkeley BOOM project is hitting really good DMIPS/MHz numbers. LowRISC has some interesting memory tagging and "minion core" ideas, etc. Edit: I left out perhaps the most important reason RISCV has a lot of hype. They've been successful getting first class support from the Linux kernel maintainers.
- pjc50 6y ago
  > quit paying ARM a percentage The percentage is very small, though. So this argument only works for very high volume use cases, which is why the RISC-V eval boards are currently far more expensive than comparable ARMs. Do WD do their own silicon yet, or do they just buy the parts?
  - Narishma 6y ago
    They design them. I don't know if they make them or not.
  - reportingsjr 6y ago
    How many ARM microcontrollers are low volume? Pretty much all of the examples I can think of are incredibly high volume. STM32, SAMD21/51, i.MX, etc. WD said they were finishing taping out their first production design about a year and a half ago, so I assume they have started shipping them at this point, but it's hard to find info.
  - nickik 6y ago
    WD has their own cores and they are OpenSource. Very nice designs. They also spend a lot of money on the open source ecosystem for chip development. See: - https://www.westerndigital.com/company/innovations/risc-v https://www.westerndigital.com/company/innovations/risc-v - https://chipsalliance.org/ https://chipsalliance.org/ - https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV
  - blihp 6y ago
    Hasn't WD been doing their own silicon (at least from a design standpoint, they still use someone else's fab) precisely because the 'small percentage' ARM charges matters for their margins? In a world where we have ESP-01 boards which retail for $2, even a couple of percent matters.
ansible 6y ago
> Is there anything about RISC-V that is "better" simply because it is a later design than others? A lot of it is because it is newer, and the designers have learned from previous architectures. It is a relatively clean and straightforward instruction set, designed to be easily and efficiently implemented. There's not anything that is super crazy revolutionary, in contrast to the (still vaporware) Mill CPU architecture. > Is it likely to evolve faster because it is open or more modern? They have a good extension mechanism that allows relatively clean additions to the instruction set. Some of the recent ones like the vector extension aren't finalized yet. Anyone can propose their own extension. Historically, ARM might work with their most important customers to implement an extension, but good luck getting their attention if you're not already paying them millions per year.
- drewm1980 6y ago
  The mill has been in development for... 18 ~years now! Soon they will be able to hire engineers who are actually younger than the company. I wonder if there has ever been a tech company that survived so long without bringing a product to market. Duke Nukem Forever took ~14 years.
  - CyberDildonics 6y ago
    Their product is hardware patents.
    - ansible 6y ago
      I would be happy if they just released a instruction-level simulator to play around with. It would also be super-nice if they released at least a Copper or Tin core (low-end) that can be synthesized to an FPGA for people to try out.
    - acehreli 6y ago
      That's patently wrong. :) I worked for the Mill for a while The Mill is as real as it gets. EDIT: No, there is no actual CPU but the software, the compiler, the simulator, etc. exist.
IshKebab 6y ago
Compared to ARM, nothing significant. They're very similar load-store architectures. Here's a RISC-V quick reference: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/... And ARM: http://users.ece.utexas.edu/~valvano/Volume1/QuickReferenceCard.pdf http://users.ece.utexas.edu/~valvano/Volume1/QuickReferenceC... The main difference is that RISC-V is a lot more modular, so it's going to be difficult to distribute binaries for but more flexible if you're doing something completely vertical. Also a lot of the modules have bundle relatively common/easy instructions with niche/difficult ones. E.g. multiply with divide.
- hajile 6y ago
  > The main difference is that RISC-V is a lot more modular, so it's going to be difficult to distribute binaries for but more flexible if you're doing something completely vertical. Also a lot of the modules have bundle relatively common/easy instructions with niche/difficult ones. E.g. multiply with divide. I don't think it'll be worse than ARM and it's decidedly better than x86. There are SEVEN major revisions of ARMv8. Then there's v8-R, v8-M, and additional 32-bit variants of each instruction set in addition to both ARMv7 and ARMv6 which also still ship billions of chips per year. Oh, and under pressure from companies, ARM also allows custom instructions now. Those aren't just theoretical either -- Apple at least added a ton of custom matrix instructions to the M1. For x86, supporting only semi-recent processors (2006 Core or greater) leaves you still checking for support for: SSE3, SSE4, SSE4.1, SSE4a, SSE4.2, SSE5, AVX, AVX2, AVX512, XOP, AES, SHA, TBM, ABM, BMI1, BMI2, F16C, ADX, CLMUL, FMA3, FMA4, LWP, SMX, TSX, RdRand, MPX, SGX, SME, and TME. That's 29 instruction sets and not all of them have use on both Intel and AMD chips. RISC-V seems at least that cohesive. If you're shipping a general purpose CPU, you'll always have mul/div, compression, fusion (not actually instructions), privilege, single precision, double precision, bit manipulation, and probably a few others. Where you'll run into mul/div missing or no floats are microcontrollers or "Larabee" style GPU cores. In all of those cases, you'll be coding to a very specific core, so that won't really matter. Thankfully, we've had ways to specify and/or check these kinds of things for decades.
  - 6y ago
jdkticom 6y ago
One of the other replies points to the RISC-V extensions feature. I think for someone who "doesn't care about openness" would at least benefit from that in the architecture. It means the same compiler can be used to bootstrap things and simple steps can be added to greatly optimize specific types of code, like AI stuff. This board really stands out in AI performance. Also, having things open means that the supply-chain can be more stable, with less chances of a single glitch in the system halting deliveries for any time. This is driving a lot of interest in RISC-V right now.
cbm-vic-20 6y ago
The ISA is pretty nice, simple, and well documented. And since it's "open", people can create their own implementations. Like this guy, who is creating a RISC-V processor from scratch, without using an FPGA. https://www.youtube.com/playlist?list=PLEeZWGE3PwbZTypHq00G-yEX8TEI95lw4 https://www.youtube.com/playlist?list=PLEeZWGE3PwbZTypHq00G-...
yiyus 6y ago
I'm quite excited about vector instructions. The approach used in RISC-V is very refreshing coming from SIMD. But I would not expect an instant impact from a user point of view.

tyingq 6y ago

I think in the real world "No percentage of each sale payments to ARM" is what will drive RISC-V. An "open" ISA doesn't force anything else to be open. So, use cases like Western Digital, where they can quit paying ARM a percentage of every hard drive they sell, for example. As for technical advantages, each RISCV vendor has their own choice of how to implement, so it's hard to say anything broad that applies to all RISCV implementations. The Berkeley BOOM project is hitting really good DMIPS/MHz numbers. LowRISC has some interesting memory tagging and "minion core" ideas, etc. Edit: I left out perhaps the most important reason RISCV has a lot of hype. They've been successful getting first class support from the Linux kernel maintainers.

pjc50 6y ago
> quit paying ARM a percentage The percentage is very small, though. So this argument only works for very high volume use cases, which is why the RISC-V eval boards are currently far more expensive than comparable ARMs. Do WD do their own silicon yet, or do they just buy the parts?
- Narishma 6y ago
  They design them. I don't know if they make them or not.
- reportingsjr 6y ago
  How many ARM microcontrollers are low volume? Pretty much all of the examples I can think of are incredibly high volume. STM32, SAMD21/51, i.MX, etc. WD said they were finishing taping out their first production design about a year and a half ago, so I assume they have started shipping them at this point, but it's hard to find info.
- nickik 6y ago
  WD has their own cores and they are OpenSource. Very nice designs. They also spend a lot of money on the open source ecosystem for chip development. See: - https://www.westerndigital.com/company/innovations/risc-v https://www.westerndigital.com/company/innovations/risc-v - https://chipsalliance.org/ https://chipsalliance.org/ - https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV
- blihp 6y ago
  Hasn't WD been doing their own silicon (at least from a design standpoint, they still use someone else's fab) precisely because the 'small percentage' ARM charges matters for their margins? In a world where we have ESP-01 boards which retail for $2, even a couple of percent matters.

ansible 6y ago

> Is there anything about RISC-V that is "better" simply because it is a later design than others? A lot of it is because it is newer, and the designers have learned from previous architectures. It is a relatively clean and straightforward instruction set, designed to be easily and efficiently implemented. There's not anything that is super crazy revolutionary, in contrast to the (still vaporware) Mill CPU architecture. > Is it likely to evolve faster because it is open or more modern? They have a good extension mechanism that allows relatively clean additions to the instruction set. Some of the recent ones like the vector extension aren't finalized yet. Anyone can propose their own extension. Historically, ARM might work with their most important customers to implement an extension, but good luck getting their attention if you're not already paying them millions per year.

drewm1980 6y ago
The mill has been in development for... 18 ~years now! Soon they will be able to hire engineers who are actually younger than the company. I wonder if there has ever been a tech company that survived so long without bringing a product to market. Duke Nukem Forever took ~14 years.
- CyberDildonics 6y ago
  Their product is hardware patents.
  - ansible 6y ago
    I would be happy if they just released a instruction-level simulator to play around with. It would also be super-nice if they released at least a Copper or Tin core (low-end) that can be synthesized to an FPGA for people to try out.
  - acehreli 6y ago
    That's patently wrong. :) I worked for the Mill for a while The Mill is as real as it gets. EDIT: No, there is no actual CPU but the software, the compiler, the simulator, etc. exist.

IshKebab 6y ago

Compared to ARM, nothing significant. They're very similar load-store architectures. Here's a RISC-V quick reference: https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/... And ARM: http://users.ece.utexas.edu/~valvano/Volume1/QuickReferenceCard.pdf http://users.ece.utexas.edu/~valvano/Volume1/QuickReferenceC... The main difference is that RISC-V is a lot more modular, so it's going to be difficult to distribute binaries for but more flexible if you're doing something completely vertical. Also a lot of the modules have bundle relatively common/easy instructions with niche/difficult ones. E.g. multiply with divide.

hajile 6y ago
> The main difference is that RISC-V is a lot more modular, so it's going to be difficult to distribute binaries for but more flexible if you're doing something completely vertical. Also a lot of the modules have bundle relatively common/easy instructions with niche/difficult ones. E.g. multiply with divide. I don't think it'll be worse than ARM and it's decidedly better than x86. There are SEVEN major revisions of ARMv8. Then there's v8-R, v8-M, and additional 32-bit variants of each instruction set in addition to both ARMv7 and ARMv6 which also still ship billions of chips per year. Oh, and under pressure from companies, ARM also allows custom instructions now. Those aren't just theoretical either -- Apple at least added a ton of custom matrix instructions to the M1. For x86, supporting only semi-recent processors (2006 Core or greater) leaves you still checking for support for: SSE3, SSE4, SSE4.1, SSE4a, SSE4.2, SSE5, AVX, AVX2, AVX512, XOP, AES, SHA, TBM, ABM, BMI1, BMI2, F16C, ADX, CLMUL, FMA3, FMA4, LWP, SMX, TSX, RdRand, MPX, SGX, SME, and TME. That's 29 instruction sets and not all of them have use on both Intel and AMD chips. RISC-V seems at least that cohesive. If you're shipping a general purpose CPU, you'll always have mul/div, compression, fusion (not actually instructions), privilege, single precision, double precision, bit manipulation, and probably a few others. Where you'll run into mul/div missing or no floats are microcontrollers or "Larabee" style GPU cores. In all of those cases, you'll be coding to a very specific core, so that won't really matter. Thankfully, we've had ways to specify and/or check these kinds of things for decades.
- 6y ago

jdkticom 6y ago

One of the other replies points to the RISC-V extensions feature. I think for someone who "doesn't care about openness" would at least benefit from that in the architecture. It means the same compiler can be used to bootstrap things and simple steps can be added to greatly optimize specific types of code, like AI stuff. This board really stands out in AI performance. Also, having things open means that the supply-chain can be more stable, with less chances of a single glitch in the system halting deliveries for any time. This is driving a lot of interest in RISC-V right now.

cbm-vic-20 6y ago

The ISA is pretty nice, simple, and well documented. And since it's "open", people can create their own implementations. Like this guy, who is creating a RISC-V processor from scratch, without using an FPGA. https://www.youtube.com/playlist?list=PLEeZWGE3PwbZTypHq00G-yEX8TEI95lw4 https://www.youtube.com/playlist?list=PLEeZWGE3PwbZTypHq00G-...

yiyus 6y ago

I'm quite excited about vector instructions. The approach used in RISC-V is very refreshing coming from SIMD. But I would not expect an instant impact from a user point of view.