6 ms·
Also worth checking out James’s simplified version designed for the Lattice iCE40 [1][2]. [1] https://www.excamera.com/sphinx/article-j1a-swapforth.html https:
by Cieplak 6y ago
Also worth checking out James’s simplified version designed for the Lattice iCE40 [1][2].
[1] https://www.excamera.com/sphinx/article-j1a-swapforth.html https://www.excamera.com/sphinx/article-j1a-swapforth.html
[2] https://youtube.com/watch?v=rdLgLCIDSk0 https://youtube.com/watch?v=rdLgLCIDSk0
- tieze 6y agoOh, thanks so much for this pointer :)
- UncleOxidant 6y agoWill the non-simplified J1 fit/run in a larger iCE40 FPGA?
- avhon1 6y agoProbably not. iCE40 FPGAs come with up to 7,680 logic cells. The J1 was designed for a board with a Xilinx XC3S1000, which has 17,280 logic cells.
- sitkack 6y agoThere are RISC-V cores that fit in about 1k luts. One could build a NoC of RISC-V using an XCS1000.
- UncleOxidant 6y agoThis is probably because the RAM is internal to the FPGA: > A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA. I'd guess the CPU itself would easily fit into an iCE40 (given that RISC-Vs are fitting and the J1 should be simpler) with the RAM external. Several of the iCE40 boards have external RAMs
- kelu124 6y agoEven the iCE UP5K has a whopping internal 1Mb RAM.