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Does optimal pipeline topology vary with the specific workload or is more dependent on the instruction set semantics and result visibility? Is this something t

Does optimal pipeline topology vary with the specific workload or is more dependent on the instruction set semantics and result visibility? Is this something that could be automatically optimized via simulation? Is it something that could be made dynamic and shared across a bunch of schedulers so that cores could move between big/little during execution.

Symmetry 6y ago
It's highly dependent on both workload and instruction set. I'm sure it could be automatically optimized in theory, even without the solution being AI complete, but I don't think we have any idea how to do it right now. No, not unless you're reflashing an FPGA. You'd have better luck sharing subcores for threadlets I think.