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It's a bit harder than that. You have to worry about forwarding results from one pipeline to another bypassing the registers if you want to avoid having to dea
by Symmetry 6y ago
It's a bit harder than that. You have to worry about forwarding results from one pipeline to another bypassing the registers if you want to avoid having to deal with stalls waiting for results. The transistor cost of the bypass network grows as the square of the number of pipelines so it can be pretty significant, potentially being larger than the cost of the execution pipelines themselves.
Many modern designs aren't fully bypassed and involve clusters of pipelines to manage this. IBM's recent Power chips and Apple's ARM cores are particularly known to do this.
- sitkack 6y agoDoes optimal pipeline topology vary with the specific workload or is more dependent on the instruction set semantics and result visibility? Is this something that could be automatically optimized via simulation? Is it something that could be made dynamic and shared across a bunch of schedulers so that cores could move between big/little during execution.
- Symmetry 6y agoIt's highly dependent on both workload and instruction set. I'm sure it could be automatically optimized in theory, even without the solution being AI complete, but I don't think we have any idea how to do it right now. No, not unless you're reflashing an FPGA. You'd have better luck sharing subcores for threadlets I think.