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RISC-V is designed to be super simple to implement, this means simple instructions that do one thing, like add or multiply. In a more complex design you have a
by quelsolaar 6y ago
RISC-V is designed to be super simple to implement, this means simple instructions that do one thing, like add or multiply. In a more complex design you have add and multiply, but also add-multiply that does both. By having that more complex instruction you can get more work done on a single instruction, but it requires more silicon.
If your goal is: build a CPU that is as simple as possible, with as few gates as possible then RISC-V is great, But if you are trying to get good performance, then RISC-v is a bad design. I think RISC-V is great, and i think it will se a lot of sucsess, because there are many applications for a slow, simple and free CPU, but it wont compete with x86 and ARM on performance.
- socialdemocrat 6y agoI don't think you quite appreciate how clever RISC-V has been designed. RISC-V is very well designed to be used with both complex and simple micro-architectures. By combining instruction compression and macro and micro-fusion you get everything you claim only x86 and ARM can do an more. Here is a proper explanation of how: https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6 https://erik-engheim.medium.com/the-genius-of-risc-v-micropr...
- Dylan16807 6y agoHow many architectures bother with a non-SIMD multiply and accumulate? I don't think it's a big issue to be missing the single form. RISC-V's vector instructions have it.
- brucehoult 6y agoAnything that claims to implement IEEE 748-2008 must have the floating point multiply-accumulate instructions. RISC-V Rocket has had those for half a dozen years already, as has any other RISC-V core with the F/D extensions.