8 ms·
> you'd have to reinvent the world to do them It reminds me of how MIPS branching is wasted on nops: https://electronics.stackexchange.com/questions/28444/mip
by 1996 6y ago
> you'd have to reinvent the world to do them
It reminds me of how MIPS branching is wasted on nops:
https://electronics.stackexchange.com/questions/28444/mips-pic32-branch-vs-branch-likely https://electronics.stackexchange.com/questions/28444/mips-p...
"The trick in writing efficient code is to put in an instruction that will be useful as part of the loop that is being taken executed, but do no harm if the branch is not taken.
The MIPS designers were counting on compiler writers to write clever enough code generators to handle this efficiently. However many do not (including Microchips C32 compiler, based on GCC), and just put NOP's after every branch, wasting both code space and cycles"
- ekiwi 6y agoThe problem with delay slots is that their optimal size is somewhat tied to the particular micro-architecture. I.e., different MIPS CPU implementations would have different optimal branch delay slot sizes. This doesn't matter too much if your compiler is allowed to optimize for your particular implementation, but we are still mostly shipping binaries and thus you would have to make trade-offs for portability reasons.
- Veedrac 6y agoThey're also pointless once you do even a small amount of dynamic local reordering, which every fast CPU does.