4 ms·

Lattice has a worship $10 iCE40 series. I'm playing with iCE40HX8K at the moment (Olimex iCE40HX8K-EVB board). I was able to configure a RV32I based SoC with AP

by ruslan 6y ago

Lattice has a worship $10 iCE40 series. I'm playing with iCE40HX8K at the moment (Olimex iCE40HX8K-EVB board). I was able to configure a RV32I based SoC with APB3, UART, Timer, RAM and SDRAM controller that fits in 2500 LUTs. I'm using SpinalHDL, which appeared to be a very convenient object oriented way of defining your hardware. SpinalHDL is a Scala based HDL language (Chisel from HiFive is another one, also Scala based) that compiles to a very long Verilog file which you then feed to IceStorm toolchain (Yosys) to synthesize bitstream for FPGA. It also allows to incorporate RV32I binary which deploys right into BRAM of your FPGA after startup. I think iCE40 is a very good FPGA to start learning open source design tools.

ekiwi 6y ago
In case you have a FOMU and are interested in exploring Chisel, I recently added a simple Blink example that should help people get started: https://github.com/im-tomu/fomu-workshop/blob/master/chisel/blink/src/Blink.scala https://github.com/im-tomu/fomu-workshop/blob/master/chisel/...
- ruslan 6y ago
  Thanks, will check it. I'm playing with FPGAs for a couple of weeks only, RISCV was a starting force for me. Currently am trying to figure our which is better SpinalHDL or Chisel. I find SpinalHDL's syntax more convenient and less verbose, but Chisel has way larger support from HiFive surrounding community.
  - ekiwi 6y ago
    I think in general Chisel has more people working on it. However, most people using Chisel are targeting ASICs, thus Spinal HDL wins when it comes to supporting features that are important to FPGAs. Chisel also hasn't anything close to the awesome VexRiscV core which was developed for FPGAs. The most developed cores written in Chisel are much bigger and more complex as they target ASICs. See the chipyard repository which tries to lower the learning curve a little bit : https://github.com/ucb-bar/chipyard/ https://github.com/ucb-bar/chipyard/
    - ruslan 6y ago
      This is very interesting. I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. Though I have not played with BOOM yet, cannot say how deeply can it be configured. But you seem right, BOOM does not look like most effective in terms of LUTs utilisation core. Another thing I also disliked in Chisel3 is dependancy on new intermediate representation of hardware (FIRRTL) which adds one more layer of abstraction and compilation.
      - ekiwi 6y ago
        > I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. It is a lot more advanced and thus harder to get started with than VexRiscV. > BOOM does not look like most effective in terms of LUTs utilisation core. So the problem is also that the BOOM design is targeted at ASICs. The developers do not generally synthesize BOOM for FPGA. Only as a FireSim project which is using FPGAs to do fast simulations in order to get more accurate performance figures by running real world benchmarks (multiple MHz of target frequency). None of the developers are interested in using BOOM as a computer on an FPGA and thus no one has provided support for that. > Another thing I also disliked in Chisel3 is dependancy on new intermediate representation of hardware (FIRRTL) which adds one more layer of abstraction and compilation. I really enjoy working with firrtl. It is generally easy to inspect and quite human readable. With firrtl you can: - automatically add coverage instrumentation: - for fuzzing: https://github.com/ekiwi/rfuzz/tree/master/instrumentation/src/rfuzz - for simulator independent coverage [wip]: https://github.com/freechipsproject/treadle/pull/263 - besides Verilog the firrtl compiler can generate SMTLib or btor2 file for model checking: https://github.com/chipsalliance/firrtl/tree/master/src/main/scala/firrtl/backends/experimental/smt https://github.com/chipsalliance/firrtl/tree/master/src/main... - for ASIC development it is important to be able to replace all memories in your design with appropriate designs specific to the technology you target: https://chipyard.readthedocs.io/en/latest/Tools/Barstools.html#mapping-technology-srams-macrocompiler https://chipyard.readthedocs.io/en/latest/Tools/Barstools.ht... Adam's thesis has some more examples on what you can do with firrtl: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-168.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-... There also might soon be a second implementation of a firrtl to Verilog compiler if you prefer C++ over Scala: https://github.com/llvm/circt https://github.com/llvm/circt
throwaway08320 6y ago
worship?
- ruslan 6y ago
  I meant famous among FOSS community, of course.
  - snvzz 6y ago
    Due to icestorm's timing, it is now the FPGA family with most mature open flow support. They're also cheap and have cheap OSHW development boards, which helps. Besides iCE40 (project icestorm), there's also ECP5 (project trellis) and quicklogic eFPGA (support provided by vendor itself!), all in good shape. Then there's some more, like GW1N (project apicula) and Xilinx family 7 (project x-ray), in a partially-working state.

by ruslan 6y ago

ekiwi 6y ago

In case you have a FOMU and are interested in exploring Chisel, I recently added a simple Blink example that should help people get started: https://github.com/im-tomu/fomu-workshop/blob/master/chisel/blink/src/Blink.scala https://github.com/im-tomu/fomu-workshop/blob/master/chisel/...

ruslan 6y ago
Thanks, will check it. I'm playing with FPGAs for a couple of weeks only, RISCV was a starting force for me. Currently am trying to figure our which is better SpinalHDL or Chisel. I find SpinalHDL's syntax more convenient and less verbose, but Chisel has way larger support from HiFive surrounding community.
- ekiwi 6y ago
  I think in general Chisel has more people working on it. However, most people using Chisel are targeting ASICs, thus Spinal HDL wins when it comes to supporting features that are important to FPGAs. Chisel also hasn't anything close to the awesome VexRiscV core which was developed for FPGAs. The most developed cores written in Chisel are much bigger and more complex as they target ASICs. See the chipyard repository which tries to lower the learning curve a little bit : https://github.com/ucb-bar/chipyard/ https://github.com/ucb-bar/chipyard/
  - ruslan 6y ago
    This is very interesting. I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. Though I have not played with BOOM yet, cannot say how deeply can it be configured. But you seem right, BOOM does not look like most effective in terms of LUTs utilisation core. Another thing I also disliked in Chisel3 is dependancy on new intermediate representation of hardware (FIRRTL) which adds one more layer of abstraction and compilation.
    - ekiwi 6y ago
      > I thought Berkeley's BOOM is way more advanced implementation of RISCV than VexRiscV and it is written in Chisel3. It is a lot more advanced and thus harder to get started with than VexRiscV. > BOOM does not look like most effective in terms of LUTs utilisation core. So the problem is also that the BOOM design is targeted at ASICs. The developers do not generally synthesize BOOM for FPGA. Only as a FireSim project which is using FPGAs to do fast simulations in order to get more accurate performance figures by running real world benchmarks (multiple MHz of target frequency). None of the developers are interested in using BOOM as a computer on an FPGA and thus no one has provided support for that. > Another thing I also disliked in Chisel3 is dependancy on new intermediate representation of hardware (FIRRTL) which adds one more layer of abstraction and compilation. I really enjoy working with firrtl. It is generally easy to inspect and quite human readable. With firrtl you can: - automatically add coverage instrumentation: - for fuzzing: https://github.com/ekiwi/rfuzz/tree/master/instrumentation/src/rfuzz - for simulator independent coverage [wip]: https://github.com/freechipsproject/treadle/pull/263 - besides Verilog the firrtl compiler can generate SMTLib or btor2 file for model checking: https://github.com/chipsalliance/firrtl/tree/master/src/main/scala/firrtl/backends/experimental/smt https://github.com/chipsalliance/firrtl/tree/master/src/main... - for ASIC development it is important to be able to replace all memories in your design with appropriate designs specific to the technology you target: https://chipyard.readthedocs.io/en/latest/Tools/Barstools.html#mapping-technology-srams-macrocompiler https://chipyard.readthedocs.io/en/latest/Tools/Barstools.ht... Adam's thesis has some more examples on what you can do with firrtl: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-168.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-... There also might soon be a second implementation of a firrtl to Verilog compiler if you prefer C++ over Scala: https://github.com/llvm/circt https://github.com/llvm/circt

throwaway08320 6y ago

worship?

ruslan 6y ago
I meant famous among FOSS community, of course.
- snvzz 6y ago
  Due to icestorm's timing, it is now the FPGA family with most mature open flow support. They're also cheap and have cheap OSHW development boards, which helps. Besides iCE40 (project icestorm), there's also ECP5 (project trellis) and quicklogic eFPGA (support provided by vendor itself!), all in good shape. Then there's some more, like GW1N (project apicula) and Xilinx family 7 (project x-ray), in a partially-working state.