3 ms·
As a historical note, the Pentium P6 uses an interesting approach. It has three decoders but only one of them can handle "complex macroinstructions" that requir
by kens 6y ago
As a historical note, the Pentium P6 uses an interesting approach. It has three decoders but only one of them can handle "complex macroinstructions" that require micro-operations from the ROM. If a limited-functionality decoder got the complex instruction, the instruction gets redirected to another decoder the next cycle.
As far as variable-length instructions, a separate Instruction Length Decoder sorts that out before decoding.
Ref: "Modern Processor Design" p268.
- 95014_refugee 6y agoThey were still doing this in the Nehalem timeframe (possibly influence from Hinton?)
- happycube 6y agoProbably should check Abner's guide, but the P6 is still the rough blueprint for everything (except P4) that intel did since.
- Dylan16807 6y ago> As far as variable-length instructions, a separate Instruction Length Decoder sorts that out before decoding. And how fast is that able to run on x86? How many instructions can that process at once, compared to an alternate universe where that circuit has the same transistor and time budget but only has to look at the first four bits of an instruction?