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People always get the idea that removing the cruft will make the design faster, and yet most of the top 500 supercomputers use x86-64 chips: https://en.wikiped
by msla 6y ago
People always get the idea that removing the cruft will make the design faster, and yet most of the top 500 supercomputers use x86-64 chips:
https://en.wikipedia.org/wiki/TOP500 https://en.wikipedia.org/wiki/TOP500
> As of November 2020, all supercomputers on TOP500 are 64-bit, mostly based on CPUs using the x86-64 instruction set architecture (of which 459 are Intel EMT64-based and 22 are AMD AMD64-based. The few exceptions are all based on RISC architectures). Thirteen supercomputers, including the no 2. and no. 3 are based on the Power ISA used by IBM POWER microprocessors, three on Fujitsu-designed SPARC64 chips. One computer uses another non-US design, the Japanese PEZY-SC (based on the British ARM[8]) as an accelerator paired with Intel's Xeon.
There are non-x86 architectures in the TOP500, including ones which have less cruft than x86, but the x86 chips keep on being used in some of the fastest machines on the planet. My hypothesis is that x86 cruft doesn't really matter, and you'd need to go to a cruft level that was orders-of-magnitude worse for the ISA choice to dominate performance.
- imtringued 6y agoIt really doesn't matter. The biggest benefit of ARM are the fixed length instructions and only Apple is actually taking advantage of this by decoding 8 instructions at once. The big question is whether decoding that many instructions is actually a benefit. It's entirely possible that branch prediction and other factors are greater bottlenecks that have to be tackled first to take advantage of the faster instruction decoding. Intel's Pentium processors (the original ones) were doing pretty badly because they made the pipeline too deep at the expense of other things.
- hajile 6y agoAnandtech's article indicates they have an out-of-order buffer of around 630 entries (Zen 3 is only 256 entries). The M1 has 7 integer math ports and 4 FP/SIMD math ports plus several bunch of load/store/branch ports . It seems like they could completely saturate those decoders given the right code.
- gpderetta 6y agoI think the original Pentium had the pretty much canonical 5 stage pipeline. It did pretty well. Its successor, the Pentium Pro, an OoO design, was deeper but also did amazingly well. You are probably thinking of the Pentium 4 which was designed as a speed demon with a very deep pipeline and failed to reach its target frequency.
- klelatti 6y agoFair points, but I think we can be 100% certain that Apple has modelled this and made their architectural decisions based on this modelling - especially as they are no the 10th or so iteration of their designs.
- rbanffy 6y agoThat and that their CPUs are designed to run one OS and apps are developed against one set of libraries. This frees them to tune the hardware to the needs of the software much more than any other manufacturer can do (a PC needs to run Word and Autocad equally well)
- klelatti 6y agoThey have certainly optimised against some key aspects of their software (eg Rosetta and reference counting) but that is not at the expense of other software. The M1 Arm CPUs are just very fast general purpose CPUs. Word and Autocad also run on the Mac!
- rbanffy 6y ago> but that is not at the expense of other software It's always at the expense of something. Transistor budget is fixed.
- rbanffy 6y agoIt's probably that x86 has a better cost/performance than others. If you can get the job that'd require, say, 200 POWERs or 250 SPARC64s with 300 Xeons that cost half per socket than a POWER, x86 will still be a better choice. This could be for many reasons - from intrinsic performance of the CPU to the quality of the code generated by the compiler and/or architectural fitness to the task at hand. Also, take into account the CPUs are not always the more expensive part of the compute node - GPUs, HBM, lots of DDR4, and fast networking gear are also pretty expensive and will be more or less constant as you change CPU architectures.